PLL702-01

Clock Generator for PowerPC Based Applications

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 07/18/05 Page 3

USB OUTPUT FREQUENCY AND CPU DRIVE STRENGTH SELECTION TABLES

USB_SEL

USB

CPUDRV_SEL

CPU drive strength

0

48 MHz

0

67% (reduced)

M

30 MHz

1

100% (nominal)

1

12 MHz

SPREAD SPECTRUM SELECTION TABLE

SSC1

SSC0

Spread Spectrum Modulation

0

0

OFF

0

1

- 0.50% – Downspread

1

0

- 1.00% – Downspread

1

1

- 1.25% – Downspread

FUNCTIONAL DESCRIPTION

Tri-level and two-level inputs

In order to reduce pin usage, the PLL702-01 uses tri-level input pins. These pins allow 3 levels for input selection: namely, 0 =

Connect to GND, 1 = Connect to VDD, M = Do not connect. Thus, unlike the two-level selection pins, the tri-level input pins are

in the “M” (mid) state when not connected. In order to connect a tri-level pin to a logical “zero”, the pin must be connected to

GND. Likewise, in order to connect to a logical “one”, the pin must be connected to VDD.

Connecting a bi-directional pin

The PLL702-01 also uses bi-directional pins. The same pin serves as input upon power-up, and as output as soon as the inputs

have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can

be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in

order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-

up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin

and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-

directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up

resistor. Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up

resistor may not be sufficient to pull the input up to a logical “one”, and an external pull-up resistor may be required.

For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the

internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the

pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is

recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application

Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this

resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may

have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical “zero”. This is

particularly true when driving 74FXX TTL components.