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PLL701-31SCL-R 数据表(PDF) 1 Page - PhaseLink Corporation

部件名 PLL701-31SCL-R
功能描述  Low EMI Spread Spectrum Multiplier Clock
PDF  5 Pages
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制造商  PLL [PhaseLink Corporation]
网页  http://www.phaselink.com
标志 PLL - PhaseLink Corporation

PLL701-31SCL-R 数据表(HTML) 1 Page - PhaseLink Corporation

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PLL701-31
Low EMI Spread Spectrum Multiplier Clock
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 11/28/05 Page 1
FEATURE
• Spread Spectrum Clock Generator with 1x
outputs.
• Output frequency ranges: 10MHz to 30MHz.
• Accepts input from crystal or reference clock.
• Selectable Center, Down or Asymmetric Spread
Modulation.
• Selectable Modulation magnitude.
• TTL/CMOS compatible outputs.
• 3.0V (+/-10%) Supply Voltage.
• Low short-term jitter.
• Available in 8-Pin 150mil SOIC.
DESCRIPTION
The PLL701-31 is a Spread Spectrum Clock
Generator designed to reduce EMI in high-speed
digital systems. The device is designed to operate
from a crystal or reference clock input and provides a
1x modulated clock output. Center, Down and
Asymmetric spread types are selectable as well as
the modulation magnitude.
PIN CONFIGURATION
Note:
^: Internal pull-up resistor (120k
Ω for SD, 30 kΩ for
SC0-SC2).
*: The value of SD is latched upon power-up. The
internal pull-up resistor results in a default high value
when no pull-down resistor is connected to this pin
(recommended external pull-down resistor of 27 k
Ω).
OUTPUT CLOCK SELECTION
SST Modulation
SD
SC2
SC1
SC0
Magnitude
Freq.
Type
0
1
1
0
3.75%
D
-3.75%
1
0
0
1
3.50%
D
-3.50%
1
0
1
0
3.75%
A
+0.125%, -3.625%
1
1
0
0
3.25%
D
-3.25%
1
1
0
1
3.50%
A
+0.125%, -3.375%
1
1
1
0
3.75%
A
+0.25%, -3.5%
0
0
0
0
3.25%
C
+/-1.625 %
0
0
0
1
3.50%
C
+/-1.75%
0
0
1
0
3.75%
C
+/-1.875%
0
0
1
1
0.00%
Fin / 512
SST OFF
Notes: A: Asymmetric Spread. D: Down Spread. C: Center Spread.
1
2
3
45
6
7
8
XIN/FIN
XOUT/SD*^
SC0^
SC1^
VDD
FOUT
GND
SC2^
XIN/FIN = 10 ~ 30 MHz


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