PLL130-07

High Speed Translator Buffer to CMOS (Selectable Drive)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 2

PIN DESCRIPTION

Name

8pin SOIC

Pin number

3x3mm QFN

Pin number

Type

Description

GND

1,3,6

1,2,4,5,

9,14,15

P

Ground.

VDD

4,7

7,10,11,12

P

Power supply.

DRIV_SEL

8

13

I

Drive Select input: ‘1’ for standard drive, ‘0’ for hi-drive output.

Internal pull-up (default is ‘1’).

REF_IN

2

3

I

Reference input signal. The frequency of this signal will be

reproduced at the output (after translation to CMOS level).

CLK_OUT

5

8

O

CMOS clock output.

OE

N/A

16

I

Output enable (‘1’ for enable). Internal pull-up (default is ‘1’).

ELECTRICAL SPECIFICATIONS

1. Absolute Maximum Ratings

PARAMETERS

SYMBOL

MIN.

MAX.

UNITS

Supply Voltage

4.6

V

Input Voltage, dc

-0.5

V

Output Voltage, dc

-0.5

V

Storage Temperature

-65

150

°C

Ambient Operating Temperature*

-40

85

°C

Junction Temperature

125

°C

Lead Temperature (soldering, 10s)

260

°C

ESD Protection, Human Body Model

2

kV

Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the

device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-

ditions above the operational limits noted in this specification is not implied.

* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.

2. AC Specifications

PARAMETERS

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Input Frequency

0

200

MHz

Input signal swing

REF_IN input

100

mV

Output Frequency

0

200

MHz