PLL130-07QC-R datasheet(3/5 Pages) PLL

部件名	PLL130-07QC-R

功能描述	High Speed Translator Buffer to CMOS (Selectable Drive)

PDF	5 Pages

Scroll/Zoom	100%

制造商	PLL [PhaseLink Corporation]

网页	http://www.phaselink.com

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3 / 5 page

PLL130-07

High Speed Translator Buffer to CMOS (Selectable Drive)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 3

3. CMOS Output Electrical Specifications

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Output High Voltage

VOH

IOH = -12mA

2.4

Output Low Voltage

VOL

ILO = 12mA

0.4

Output High Voltage at CMOS

level

VOHC

IOH = -4mA

VDD– 0.4

At TTL level (High drive*)

Output drive current

At TTL level (Standard drive)

* Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN).

4. CMOS Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

0.8V ~ 2.0V with 10 pF load

1.15

Output Clock Rise/Fall Time

0.3V ~ 3.0V with 15 pF load

3.7

0.8V ~ 2.0V with 10 pF load

0.5

Output Clock Rise/Fall Time

(High Drive*)

0.3V ~ 3.0V with 15 pF load

1.5

* Note: High Drive CMOS is selectable through DRIV_SEL selector input on pin 8(SOIC) or 13(QFN).

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