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PLL502-35OC-R 数据表(PDF) 4 Page - PhaseLink Corporation |
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PLL502-35OC-R 数据表(HTML) 4 Page - PhaseLink Corporation |
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4 / 9 page ![]() PLL502-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier VCXO Universal Low Phase Noise IC’s 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 01/19/06 Page 4 2. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Crystal Resonator Frequency FXIN Parallel Fundamental Mode 12 25 MHz Crystal Loading Rating CL (xtal) At VCON = 1.65V 9.5 pF Crystal Pullability C0/C1 (xtal) AT cut 250 - Recommended ESR RE AT cut 30 Ω Note: Crystal Loading rating: 9.5pF is the loading the crystal sees from the VCXO chip at VCON = 1.65V. It is assumed that the crystal will be at nomi- nal frequency at this load. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 3. Voltage Control Crystal Oscillator PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS VCXO Stabilization Time * TVCXOSTB From power valid 10 ms VCXO Tuning Range FXIN = 12 – 25MHz; XTAL C0/C1 < 250 0V ≤ VCON ≤ 3.3V 500 ppm CLK output pullability VCON=1.65V, ±1.65V ±200 ppm VCXO Tuning Characteristic 150 ppm/V Pull range linearity 10 % VCON pin input impedance 2000 k Ω VCON modulation BW 0V ≤ VCON ≤ 3.3V, -3dB 25 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. General Electrical Specifications PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Fout<24MHz 60/28/15 24MHz<Fout<96MHz 65/45/30 Supply Current, Dynamic (with Loaded Outputs) IDD PECL/LVDS/CMOS 96MHz<Fout<800MHz 100/80/40 mA Operating Voltage VDD 2.97 3.63 V Output Clock Duty Cycle @ 50% VDD (CMOS) @ 1.25V (LVDS) @ VDD – 1.3V (PECL) 45 45 45 50 50 50 55 55 55 % Short Circuit Current ±50 mA |
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