PLL520-17/-18/-19

Low Phase Noise VCXO with multipliers (for 65-130MHz Fund Xtal)

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/20/04 Page 6

10. PECL Electrical Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

MAX.

UNITS

Output High Voltage

V

Output Low Voltage

(see figure)

V

11. PECL Switching Characteristics

PARAMETERS

SYMBOL

CONDITIONS

MIN.

TYP.

MAX.

UNITS

Clock Rise Time

@20/80% - PECL

0.6

1.5

ns

Clock Fall Time

@80/20% - PECL

0.5

1.5

ns

PACKAGE INFORMATION

C

L

A

16 PIN Narrow SOIC, TSSOP ( mm )

SOIC

TSSOP

Symbol

Min.

Max.

Min.

Max.

A

1.35

1.75

-

1.20

A1

0.10

0.25

0.05

0.15

B

0.33

0.51

0.19

0.30

C

0.19

0.25

0.09

0.20

D

9.80

10.00

4.90

5.10

E

3.80

4.00

4.30

4.50

H

5.80

6.20

6.40 BSC

L

0.40

1.27

0.45

0.75

e

1.27 BSC

0.65 BSC

E

H

D

A

1

e

B

OUT

OUT

50

Ω

50

Ω

PECL Levels Test Circuit

PECL Transistion Time Waveform

OUT

OUT

50%

20%

80%

t

R

t

F

VDD

DUTY CYCLE

45 - 55%

55 - 45%

50%

OUT

OUT

t

SKEW

PECL Output Skew

2.0V