STCC02-ED5

4/13

The Zero Voltage Synchronization ZVS circuit generates a low frequency clock using the AC line cycles

(20 ms on 50 Hz or 16.7 ms on 60 Hz). This clock allows the MCU to generate the cooking timings and to

reduce the magnetron inrush current by powering it on at the AC line peak voltage.

The input pin SYN is an image of the mains voltage and is usually connected to the supply transformer

The circuit is protected against fast line transients because its state change will act on the whole MCU

routines: a 30

µs filter is implemented giving a higher immunity to the MCU circuit.

Since the ZVS pin connected to the Non Maskable Interrupt NMI or INT\ of the MCU, its falling edge is the

active counting event. The delay between the real Zero Crossing event and this ZVS falling edge depends

ply load and the temperature. The STCC02 contribution to this delay can be evaluated by measuring the

The magnetron of the oven can be powered only if the door is closed in order to protect the oven user.

This safety feature is ensured mechanically by putting the door switch in series with the magnetron relay

coil supply.

For redundancy purpose, the Door Closed Detection CDD signal is also transmitted to the MCU. Since the

DS input detects the door state from an electromechanical switch, a spike suppressor is added to increase

its robustness. Its EMI immunity in off state (open door) is increased thanks to a 50k

Ω pull down resistor

that maintains the DS signal in low state. When DS is high (24V), CDD signal is also in high state (5V).

50µs

115µs

50µs

50µs

115µs

115µs

CC

CC

= 10 k ; V

= 15 V; I

= 20 mA

Ω

FALLING EDGE

RISING EDGE

2V / div

40µs / div

DS

Door Switch

EMI Filter

500

Ω

50 k

Ω

25 k

Ω