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ICS5250708 数据表(PDF) 4 Page - Integrated Circuit Systems |
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ICS5250708 数据表(HTML) 4 Page - Integrated Circuit Systems |
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4 / 9 page ![]() LVCMOS User Configurable Clock MDS 525-07/08 A 4 Revision 101105 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS525-07/08 PRELIMINARY INFORMATION Output Frequency and Output Divider Table (ICS525-07) Output Frequency and Output Divider Table (ICS525-08) S2 Pin 5 S1 Pin 4 S0 Pin 3 CLK Output Divider Output Frequency Range (MHz) VDD = 2.5 V VDD = 1.8 V Min Max Min Max 0 0 0 12 8.3 20.8 8.3 20.8 0 0 1 2 50 125 50 125 0 1 0 16 6.25 15.63 6.25 15.63 0 1 1 4 25 62.5 25 62.5 1 0 0 5 20 50 20 50 1 0 1 7 14.3 35.7 14.3 35.7 1 1 0 1 100 250 100 250 1 1 1 3 33.3 83.33 33.3 83.33 S3 Pin 2 S2 Pin 5 S1 Pin 4 S0 Pin 3 CLK Output Divider Output Frequency Range (MHz) VDD = 2.5 V VDD = 1.8 V Min Max Min Max 0 0 0 0 2 23.9 200 23.9 200 0 0 0 1 3 15.9 200 15.9 200 0 0 1 0 4 11.9 200 11.9 200 0 0 1 1 5 9.5 158.4 9.5 158.4 0 1 0 0 7 6.8 113.1 6.8 113.1 01 01 8 6.0 99.0 6.0 99.0 01 10 9 5.3 88.0 5.3 88.0 0 1 1 1 10 4.8 79.2 4.8 79.2 1 0 0 0 11 4.3 72.0 4.3 72.0 1 0 0 1 13 3.7 60.9 3.7 60.9 1 0 1 0 14 3.4 56.6 3.4 56.6 1 0 1 1 15 3.2 52.8 3.2 52.8 1 1 0 0 17 2.8 46.6 2.8 46.6 1 1 0 1 19 2.5 41.7 2.5 41.7 1 1 1 0 48 1.0 16.5 1.0 16.5 1 1 1 1 128 0.4 6.2 0.4 6.2 |
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