LVCMOS User Configurable Clock

MDS 525-07/08 A

7

Revision 101105

Integrated Circuit Systems, Inc.

ICS525-07/08

PRELIMINARY INFORMATION

AC Electrical Characteristics

Unless stated otherwise, VDD = 1.8 V to 2.5 V

NOTE 1: Phase relationship between input and output can change at power-up.

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

Crystal input

5

27

MHz

Clock input

2

50

MHz

Output Frequency (ICS525-07)

-40 to +85

°C10

200

MHz

Output Frequency (ICS525-08)

-40 to +85

°C0.4

200

MHz

Output Clock Rise Time

20% to 80%

1

ns

Output Clock Fall Time

80% to 20%

1

ns

Output Clock Duty Cycle

at VDD/2

45

49 to 51

55

%

Power-down Time, PD low to

clocks stopped

50

ns

Power-up Time, PD high to

clocks stable

5ms

Absolute Clock Period Jitter,

VDD = 2.5 V

Deviation from mean

ps

One Sigma Clock Period Jitter,

VDD = 2.5 V

One Sigma

ps

Absolute Clock Period Jitter,

VDD = 1.8 V

Deviation from mean

ps

One Sigma Clock Period Jitter,

VDD = 1.8 V

One Sigma

ps