Triple PLL Field Programmable VCXO Clock Synthesizer

MDS 271 A

6

Revision 040705

Integrated Circuit Systems, Inc.

ICS271

PRELIMINARY INFORMATION

Note 1: Example with 25 MHz crystal input with six outputs of 33.3 MHz, no load, and VDD = 3.3 V.

AC Electrical Characteristics

Unless stated otherwise, VDD, VDDO = 3.3 V ±5%, Ambient Temperature -40 to +85

° C

Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.

Note 2: Measured with 15 pF load, VDDO = 3.3 V at VDDO/2.

Note 3: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%

Internal pull-up Resistor

S2:S0, PDTS

190

k

Ω

Internal pull-down

Resistor

CLK outputs

120

k

Ω

Input Capacitance

Inputs

4

pF

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units

Input Frequency

Fundamental crystal

5

27

MHz

Output Frequency

VDDO=VDD

0.314

200

MHz

1.8V<VDDO<2.8

0.314

150

MHz

Crystal Pullability

0V< VIN < 3.3 V, Note 1,

Config. Dependent

100

ppm

VCXO Gain

VIN = VDD/2 + 1 V,

Note 1, Config.

Dependent

120

ppm/V

Output Rise/Fall Time

80% to 20%, high drive,

Note 2

1.0

ns

Output Rise/Fall Time

80% to 20%, low drive,

Note 2

2.0

ns

Output Clock Duty Cycle,

VDDO = 3.3 V

Note 3

40

49-51

60

%

Power-up time

PLL lock-time from

power-up

410

ms

PDTS goes high until

stable CLK output

0.6

2

ms

One Sigma Clock Period Jitter

Configuration Dependent

50

ps

Maximum Absolute Jitter

Deviation from Mean.

Configuration Dependent

+200

ps

Pin-to-Pin Skew

Low Skew Outputs

-250

250

ps

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Units