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Revision 0.96

25 - 29

AS1530, AS1531

Data Sheet

Quick Evaluation Circuit

Quick Evaluation Circuit

In order to quickly evaluate the analog performance of the AS1530/AS1531, use the circuit shown in Figure 35.

Figure 35. Evaluation Circuit Diagram

= 1) on CH7 without powering down between conversions. The SSTRB output pulses high for one clock period before

the MSB of the 12-bit conversion result is shifted out of DOUT. Varying the analog input to CH7 will alter the sequence

of bits from DOUT. A total of 16 clock cycles is required per conversion.

Note:

All SSTRB and DOUT output transitions occur 25ns (typ) after the rising edge of SCLK.

+2.5V

Analog

Input

0.1µF

12

REFADJ

11

REF

4.7µF

13

GND

17

CSN

14

DOUT

15

SSTRB

18

SCLK

16

DIN

0.1µF

To

0.1µF

10µF

+3 or

+5V

External

Clock

8

CH7

AS1530/

AS1531

TBA

20

19

10

9

COM