ADUCM3027BCBZ-R7 datasheet(23/39 Pages) AD

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Data Sheet

ADuCM3027/ADuCM3029

Rev. B | Page 23 of 39

MEMORY ARCHITECTURE

The internal memory of the ADuCM3027/ADuCM3029 is

shown in Figure 22. The internal memory incorporates up to

256 kB of embedded flash memory for program code and

nonvolatile data storage, 32 kB of data SRAM, and 32 kB of

SRAM (configured as instruction space or data space).

SRAM Region

This memory space contains the application instructions and

literal (constant) data that must be accessed in real-time. It

supports read/write access by the ARM Cortex-M3 core and

read/write DMA access by system peripherals. Byte, half-word,

and word accesses are supported.

SRAM is divided into 32 kB data SRAM and 32 kB instruction

SRAM. If instruction SRAM is not enabled, then the associated

32 kB can be mapped as data SRAM, resulting in 64 kB of data

SRAM.

Parity bit error detection (optional) is available on all SRAM

memories. Two parity bits are associated with each 32-bit word.

When the cache controller is enabled, 4 kB of the instruction

SRAM is reserved as cache memory.

Users can select the SRAM configuration modes depending on

the instruction SRAM and cache needed.

In hibernate mode, 8 kB to 32 kB of the SRAM can be retained

in increments of 8 kB. 8 kB of data SRAM is always retained.

Users can additionally retain



16 kB out of 32 kB of instruction SRAM



8 kB out of 32 kB of data SRAM

MMRs (Peripheral Control and Status)

For the address space containing MMRs, refer to Figure 22.

These registers provide control and status for on-chip

peripherals of the ADuCM3027/ADuCM3029. For more

information about the MMRs, refer to the ADuCM302x Ultra

Low Power ARM Cortex-M3 MCU with Integrated Power

Management Hardware Reference.

Flash Memory

The ADuCM3027/ADuCM3029 MCUs include 128 kB to

256 kB of embedded flash memory, which is accessed using a

flash controller. For memory available on each product, see

Table 1. The flash controller is coupled with a cache controller.

A prefetch mechanism is implemented in the flash controller to

optimize code performance.

Flash writes are supported by a key hole mechanism via

advanced peripheral bus (APB) writes to MMRs. The flash

controller provides support for DMA-based key hole writes.

With respect to flash integrity, the devices support the

following:



A fixed user key required for running protected

commands, including mass erase and page erase.



An optional and user definable user failure analysis key

(FAA key). Analog Devices personnel need this key while

performing failure analysis.



An optional and user definable write protection for user

accessible memory.



8-bit ECC.

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