USB7252CTSLASHKDX datasheet(6/63 Pages) MICROCHIP

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DS00003852A-page 6

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2021 Microchip Technology Inc.

2.0

INTRODUCTION

2.1

General Description

The Microchip USB7252C hub is a low-power, OEM configurable, USB 3.2 Gen 2 hub controller with 4 downstream

ports and advanced features for embedded USB applications. The USB7252C is fully compliant with the Universal Serial

Bus Revision 3.2 Specification and USB 2.0 Link Power Management Addendum. The USB7252C supports 10 Gbps

SuperSpeed+ (SS+), 5 Gbps SuperSpeed (SS), 480 Mbps Hi-Speed (HS), 12 Mbps Full-Speed (FS), and 1.5 Mbps Low-

Speed (LS) USB downstream devices on three standard USB 3.2 Gen 2 downstream ports and only legacy speeds (HS/

FS/LS) on one standard USB 2.0 downstream port.

The USB7252C is a standard USB 3.2 Gen 2 hub that supports native basic Type-C with integrated CC logic on two

downstream ports. The downstream Type-C ports include internal USB 3.2 Gen 2 multiplexers; no external multiplexer

is required for Type-C support.

The USB7252C supports the legacy USB speeds (HS/FS/LS) through a dedicated USB 2.0 hub controller that is the

culmination of seven generations of Microchip hub feature controller design and experience with proven reliability,

interoperability, and device compatibility. The SuperSpeed hub controller operates in parallel with the USB 2.0 controller,

decoupling the 10/5 Gbps SS+/SS data transfers from bottlenecks due to the slower USB 2.0 traffic.

The USB7252C enables OEMs to configure their system using “Configuration Straps.” These straps simplify the config-

uration process assigning default values to USB 3.2 Gen 2 ports and GPIOs. OEMs can disable ports, enable battery

charging and define GPIO functions as default assignments on power up removing the need for OTP or external SPI

ROM.

The USB7252C supports downstream battery charging. The USB7252C integrated battery charger detection circuitry

supports the USB-IF Battery Charging (BC1.2) detection method and most Apple devices. The USB7252C provides the

battery charging handshake and supports the following USB-IF BC1.2 charging profiles:

• DCP: Dedicated Charging Port (Power brick with no data)

• CDP: Charging Downstream Port (1.5A with data)

• SDP: Standard Downstream Port (0.5A[USB 2.0]/0.9A[USB 3.2] with data)

Additionally, the USB7252C includes many powerful and unique features such as:

The Hub Feature Controller, an internal USB device dedicated for use as a USB to I2C/UART/SPI/GPIO interface that

allows external circuits or devices to be monitored, controlled, or configured via the USB interface.

Multi-Host Endpoint Reflector, which provides unique USB functionality whereby USB data can be “mirrored” between

two USB hosts (Multi-Host) in order to perform a single USB transaction.This capability is fully covered by Microchip

intellectual property (U.S. Pat. Nos. 7,523,243 and 7,627,708) and is instrumental in enabling Apple CarPlay™, where

the Apple iPhone® becomes a USB Host.

FlexConnect, which provides flexible connectivity options. One of the USB7252C’s downstream ports can be reconfig-

ured to become the upstream port, allowing master capable devices to control other devices on the hub.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment

of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the

PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB signal drive strength

in the downstream port transceivers. PHYBoost attempts to restore USB signal integrity

in a compromised system environment. The graphic on the right shows an example of

Hi-Speed USB eye diagrams before and after PHYBoost signal integrity restoration. in

a compromised system environment.

VariSense, which controls the Hi-Speed USB receiver sensitivity enabling programmable levels of USB signal receive

sensitivity. This capability allows operation in a sub-optimal system environment, such as when a captive USB cable is

used.

Port Split, which allows for the USB 3.2 Gen 2 and USB 2.0 portions of downstream port 3 to operate independently

and enumerate two separate devices in parallel in special applications.

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