LTC4367 datasheet(13/22 Pages) AD

13 / 22 page

LTC4249

Rev. 0

For more information www.analog.com

LOAD CURRENT (A)

0.01

0.1

100

102

104

106

108

110

–10

–8

–6

–4

–2

IMON Gain and Error

4249 F09

Figure 9. Typical IMON Gain vs Load Current

The IMON output has the bandwidth to follow ECB cur-

rents to approximately 50kHz. The bandwidth is a func-

tion of load capacitance at OUT and any capacitance at

the IMON output. Figure 10 shows how the IMON output

voltage follows a step change in ECB current from 0.5A to

1A. OUT capacitance is 100µF and no explicit capacitance

was added to IMON.

0.5A

0.5V

2ms/DIV

IMON VOLTAGE

500mV/DIV

ECB CURRENT

500mA/DIV

4249 F10

Figure 10. IMON Step Response (COUT = 100µF, RIMON = 10kΩ)

In applications where ECB current information must be

captured, the scaled ECB current history can be stored in

external memory by digitizing the IMON voltage with an

analog to digital converter.

Load Current Servo Control

In RF PA applications, the IMON voltage may be compared

to a reference and a control loop can servo the PA gate

bias to control drain bias current. The front-page applica-

tion schematic demonstrates how PA BIAS current can be

controlled by a DAC. PA VGG threshold variations due to

process and temperature are overcome with servo con-

trol, making individual bias trims obsolete.

In the front-page application, the input supply (28V) at

IN1 passes to the RF PA VDD when the voltage at EN1

exceeds 0.8V. Resistors R1 and R2 are chosen to provide

an under-voltage (UV) threshold of 24.88V and 1.09V of

falling hysteresis. Below threshold, RDY1 is low and the

op amp is in shutdown. With the op amp in shutdown,

the RF PA VGG is pulled to the negative potential (–5V)

through ROFF and the PA is off.

When the 28V input exceeds the UV threshold, the PA VDD

voltage ramps to the IN1 potential. RDY1 pulls high after

10ms and the op amp becomes active. At this point, the

op amp drives the RF PA VGG to the potential that forces

the PA BIAS current to track the controlling input at the op

amp non-inverting terminal. For example, if the control-

ling input is 1V, the PA VGG bias moves to force the PA

BIAS current to 1A.

If the PA BIAS current exceeds 1.2A, the ECB disconnects

the VDD bias and the RDY1 output pulls low. With RDY1

low, the op amp is in shutdown and the PA VGG bias pulls

to the negative rail.

For most closed loop applications, loop stability is

achieved with integrating capacitor CF. In situations where

COUT is greater than 10µF, an additional resistor/capacitor

combination may be needed for lead-lag compensation.

A generalized compensation methodology is described

below.

Loop Analysis

The front page schematic loop elements are extracted

and shown in Figure 11. Various important quantities are

defined here:

• VC: the controlling input at the non-inverting terminal

of the op amp

• RON: the ECB on-resistance (75mΩ)

• COUT: the PA VDD drain capacitance (10µF)

• GM: the LTC4249 current monitor transconductance

(1.33 mA/V)

APPLICATIONS INFORMATION

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