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ICS843021 数据表(PDF) 8 Page - Integrated Circuit Systems |
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ICS843021 数据表(HTML) 8 Page - Integrated Circuit Systems |
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8 / 13 page ![]() 843021AG www.icst.com/products/hiperclocks.html REV. C MARCH 31, 2005 8 Integrated Circuit Systems, Inc. ICS843021 FEMTOCLOCKS™CRYSTAL-TO- 3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843021. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843021 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for V CC = 3.3V + 10% = 3.63V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core) MAX = VCC_MAX * IEE_MAX = 3.63V * 85mA = 308.6mW • Power (outputs) MAX = 30mW/Loaded Output pair Total Power _MAX (3.63V, with all outputs switching) = 308.6mW + 30mW = 338.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θ JA * Pd_total + TA Tj = Junction Temperature θ JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) T A = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ JA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.339W * 90.5°C/W = 100.7°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θθθθθ JA FOR 8-PIN TSSOP, FORCED CONVECTION θθθθθ JA by Velocity (Meters per Second) 0 1 2.5 Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W NOTE: Most modern PCB designs use multi-layered boards. |
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