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ICS2402MLF 数据表(PDF) 2 Page - Integrated Circuit Systems |
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ICS2402MLF 数据表(HTML) 2 Page - Integrated Circuit Systems |
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2 / 7 page ![]() Multiplier and Zero Delay Buffer MDS 2402 D 2 Revision 122104 Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com ICS2402 Pin Assignment Clock Multiplier Decoding Table 1 (Multiplies Input clock by shown amount) Pin Descriptions ICLK NC GND VDD FBIN S0 CLK 1 2 3 4 8 7 6 5 GND NC 1 2 3 4 8 7 6 5 8 pin (150 mil) SOIC S0 CLK 0 2 X ICLK 1ICLK Pin Number Pin Name Pin Type Pin Description 1 ICLK Input Reference clock input. 2 NC — No connect. Do not connect to anything. 3 GND Power Connect to ground. 4 FBIN Input Feedback clock input. 5 NC — No connect. Do not connect to anything. 6 S0 Input Select pin for Clock Multiplier Decoding Table above. 7 VDD Power Connect to +3.3 V or +5.0 V. 8 CLK Output Clock output per table above. |
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