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AMD-751™ System Controller Revision Guide

22564B-1—February 2000

Preliminary Information

21

Potential Memory Failure When Using Certain Double-Sided SDRAM

Memory DIMMs

Products Affected. C3 and C5

Description. Under certain SDRAM double-sided DIMM loading conditions, systems based on the the

AMD-751 system controller can experience reduced timing margins, resulting in memory failures

during memory cycles.

This condition only occurs when using specific double-sided DIMMs with combinations of the following

characteristics:

1.

Printed Wiring Board (PWB) designed around the Intel LC_12_112 Gerber.

2.

Potential Effect on System. Unstable system.

Suggested Workarounds.

1.

Vendors should use memory DIMMs only from an approved vendor list (AVL). DIMMs

from this list have been extensively tested on AMD-751 based platforms and qualified for

usage. Please consult your OEM or AMD specialist for details.

2.

Vendors developing new AMD-751 based motherboards should implement pulldown

resistors on the MAA[14:0] and MAB[14:0] address buses. Use of this termination

method will improve the timing margins. Please consult your OEM or AMD specialist for

specific values.

Resolution Status. All future motherboards should be implemented with the suggested termination

method

.