DS31256+ datasheet(8/183 Pages) MAXIM

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DS31256 256-Channel, High-Throughput HDLC Controller

8 of 183

DS31256 has been designed to handle up to 132Mbps in both the receive and transmit directions without

any potential loss of data due to priority conflicts in the transfer of data from the HDLC engines to the

FIFO and vice versa.

The FIFO transfers data from the HDLC engines into the FIFO and checks to see if the FIFO has filled to

beyond the programmable high watermark. If it has, then the FIFO signals to the DMA that data is ready

to be burst read from the FIFO to the PCI Bus. The FIFO block controls the DMA block and it tells the

DMA when to transfer data from the FIFO to the PCI Bus. Since the DS31256 can handle multiple

HDLC channels, it is quite possible that at any one time, several HDLC channels will need to have data

transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the DMA will

handle next via a Host configurable algorithm, which allows the selection to be either round robin or

priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the application, the

selection of this algorithm can be quite important. The DS31256 cannot control when it will be granted

PCI Bus access and if bus access is restricted, then the host may wish to prioritize which HDLC channels

get top priority access to the PCI Bus when it is granted to the DS31256.

When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO

(even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC

packet is not large enough to fill the FIFO to the high watermark, then the FIFO will not wait for more

data to enter the FIFO, it will signal the DMA that an end-of-frame (EOF) was detected and that data is

ready to be transferred from the FIFO to the PCI Bus by the DMA.

In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC

(Layer 2) engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority

decoded with Port 0 generally getting the highest priority. Hence, if multiple ports are requesting packet

data, the FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower

numbered ports before moving on to the higher numbered ports. Again there is no potential loss of data

as long as the transmit throughput maximum of 132Mbps is not exceeded. When the FIFO detects that a

HDLC engine needs data, it then transfers the data from the FIFO to the HDLC engines in 32-bit chunks.

If the FIFO detects that the FIFO is below the low watermark, it then checks with the DMA to see if

there is any data available for that HDLC Channel. The DMA will know if any data is available because

the Host on the PCI Bus will have informed it of such via the pending-queue descriptor. When the DMA

detects that data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets

the highest priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the

DS31256 can handle multiple HDLC channels, it is quite possible that at any one time, several HDLC

channels will need the DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which

HDLC channel the DMA will handle next via a host configurable algorithm, which allows the selection

to be either round robin or priority, decoded (with HDLC Channel 1 generally getting the highest

priority).

When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with

HDLC packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA

has filled it to beyond the low watermark (or an EOF is reached), the FIFO will begin transferring 32-bit

dwords to the HDLC engine.

One of the unique attributes of the DS31256 is the structure of the DMA. The DMA has been optimized

to maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data.

The DMA uses a flexible scatter/gather technique, which allows that packet data to be place anywhere

within the 32-bit address space. The user has the option on the receive side of two different buffer sizes

DS31256+ 数据表(PDF) 8 Page - Maxim Integrated Products

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