EV-ADE9153ASHIELDZ datasheet(44/50 Pages) AD

44 / 50 page

ADE9153A

Data Sheet

Rev. 0 | Page 44 of 50

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

[4:3]

Reserved

Reserved.

0x0

ZX_OUT_OE

When this bit is set, ZX is

driven to the

CF2 pin.

0x0

R/W

DREADY_OE

When this bit is set, DREADY

is driven to the CF2 pin.

0x0

R/W

SWRST

Set this bit to initiate a

software reset. This bit is self

clearing.

0x0

0x490

CFMODE

[15:8]

Reserved

Reserved.

0x0

CF2DIS

CF2 output disable. Set this

bit to disable the CF2

output and bring the pin

high. Note that when this

bit is set, the CFx bit in the

status register is not set

when a CF pulse is

accumulated in the digital

to frequency converter.

0x0

R/W

CF1DIS

CF1 output disable. See the

CF2DIS description.

0x0

R/W

[5:3]

CF2SEL

Type of energy output on

the CF2 pin.

0x0

R/W

0 Total active power.

10 Total apparent power.

100 Fundamental reactive

power.

[2:0]

CF1SEL

Selects type of energy output

on the CF1 pin. See the

CF2SEL description.

0x0

R/W

0x492

ACCMODE

[15:5]

Reserved

Reserved.

0x0

SELFREQ

System frequency select bit. 0x0

R/W

0 50 Hz system.

1 60 Hz system.

[3:2]

VARACC

Fundamental reactive

power accumulation mode

for energy registers and CFx

pulses.

0x0

R/W

0 Signed accumulation mode.

1 Absolute value

accumulation mode.

10 Positive accumulation

mode.

11 Negative accumulation

mode.

[1:0]

WATTACC

Total active power

accumulation mode for

energy registers and CFx

pulses. See the VARACC

description.

0x0

R/W

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