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MAX9111 数据表(PDF) 2 Page - Maxim Integrated Products |
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MAX9111 数据表(HTML) 2 Page - Maxim Integrated Products |
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2 / 12 page ![]() VCC to GND..............................................................-0.3V to +4V IN_ _ to GND .........................................................-0.3V to +3.9V OUT_ _ to GND..........................................-0.3V to (VCC + 0.3V) ESD Protection All Pins (Human Body Model, IN_+, IN_-)...................................±11kV Continuous Power Dissipation (TA = +70°C) 8-Pin SOT23 (derate 5.10mW/°C above +70°C) ...408.60mW 8-Pin SO (derate 5.88mW°C above +70°C).................471mW 8-Pin TDFN (derate 6.20mW°C above +70°C) ...........496mW Operating Temperature Ranges MAX911_E.......................................................-40°C to +85°C MAX911_A .....................................................-40°C to +125°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. SOT23-8 PACKAGE CODE K8+1 Outline Number 21-0078 Land Pattern Number 90-0176 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 195.80°C/W Junction to Case (θJC) 70°C/W SO-8 PACKAGE CODE S8-2/S8+2 Outline Number 21-0041 Land Pattern Number 90-0096 Thermal Resistance, Single-Layer Board: Junction to Ambient (θJA) 170°C/W Junction to Case (θJC) 40°C/W Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 136°C/W Junction to Case (θJC) 38°C/W TDFN-8 PACKAGE CODE T822CY+2 Outline Number 21-100341 Land Pattern Number 90-100117 Thermal Resistance, Four-Layer Board: Junction to Ambient (θJA) 162°C/W Junction to Case (θJC) 20°C/W Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial. For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. Package Information MAX9111/MAX9113 Single/Dual LVDS Line Receivers with Ultra-Low Pulse Skew in SOT23 www.maximintegrated.com Maxim Integrated │ 2 |
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