MP7641

5

Rev. 2.00

ELECTRICAL CHARACTERISTICS TABLE

Description

Symbol

Min

Typ

Max

Min

Max

Units

Conditions

DIGITAL TIMING

Input Clock Pulse Width

40

50

ns

Data Setup Time

10

10

ns

Data Hold Time

15

15

ns

CLK to SDO Propagation Delay

40

50

ns

DAC Register Load Pulse Width

100

100

ns

Reset Pulse Width

50

60

ns

Clock Edge to Load Rising Edge

100

100

ns

Clock Edge to Load Falling Edge

00

ns

Load Falling Edge to SDO

50

60

ns

3-state Enable

Load Rising Edge to SDO

35

50

ns

3-state Disable

Load Falling Edge to CLK Disable

25

40

ns

Load Rising Edge to CLK Enable

35

50

ns

LD Set-up Time with Respect

15

20

ns

to CLK

25

NOTES

1

Full Scale Range (FSR) is 3V.

2

Guaranteed but not production tested.

3

Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur.

4

See Figures 2 and 3.

5

Tmin to Tmax

Specifications are subject to change without notice