ADP5091/ADP5092

Data Sheet

Rev. A | Page 8 of 28

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

2

1

3

4

5

6

18

17

16

15

14

13

SETHYST

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

SETPG

TERM

SETBK

SETSD

REF

SW

REG_OUT

REG_FB

SYS

BAT

BACK_UP

ADP5091

TOP VIEW

(Not to Scale)

Figure 3. ADP5091 Pin Configuration

2

1

3

4

5

6

18

17

16

15

14

13

SETHYST

NOTES

1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.

SETPG

TERM

SETBK

SETSD

REF

SW

REG_OUT

REG_FB

SYS

BAT

BACK_UP

ADP5092

TOP VIEW

(Not to Scale)

Figure 4. ADP5092 Pin Configuration

Table 5. Pin Function Descriptions

Pin No.1

Mnemonic

Description

ADP5091

ADP5092

1

1

REF

Internal Voltage Reference Monitoring Node for the SETSD, SETPG, SETBK, and TERM Pins.

2

2

SETSD

Shutdown Setting. The SETSD pin sets the shutdown discharging voltage based on the BAT pin

voltage level.

3

3

SETBK

BACK_UP Disabled Threshold Monitoring BAT Voltage Setting. Connect the SETBK pin to the AGND

pin without the BACK_UP storage element.

4

4

TERM

Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT pin

voltage level.

5

5

SETPG

Power-Good Rising Threshold Monitoring SYS Node Voltage Level Setting.

6

6

SETHYST

PGOOD Falling Hysteresis Setting. Connect a resistor between SETPG and SETHYST to program the

PGOOD falling hysteresis.

7

7

AGND

Analog Ground.

8

8

CBP

Capacitor Bypass. This pin samples and holds the maximum power point level. Connect a 10 nF

capacitor from the CBP pin to the AGND pin. When the MPPT pin is disabled, tie the CBP pin to an

external reference that is lower than the VIN pin.

9

9

MPPT

Maximum Power Point Tracking. This pin sets the maximum power point ratio for the different

energy harvesters with a resistor divider. In no sensing mode, place a resistor through AGND to set

the MPPT voltage. The typical current value is 2.0 µA.

10

10

VIN

Input Supply from Energy Harvester Source. Connect at least a 10 µF capacitor as close as possible

between VIN and PGND.

11

N/A

LLD

Low Light Density Indicator to Microcontroller for the ADP5091. LLD pulls high at the MINOP voltage

higher than the CBP voltage.

N/A

11

REG_GOOD

Regulated Output Power Good for the ADP5092.

12

12

PGND

Power Ground.

13

13

SW

Switching Node for the Inductive Boost Regulator with a Connection to an External Inductor.

Connect a 22 µH inductor between SW and VIN.

14

14

REG_OUT

Regulated Output. Connect at least a 4.7 µF capacitor as close as possible between REG_OUT and PGND.

15

15

REG_FB

Regulated Output Feedback Voltage Sense Input. The fixed output connects this pin to REG_OUT.

The adjustable output connects this pin to a resistor divider from REG_OUT.

16

16

SYS

Output Supply to System Load. Connect at least a 4.7 µF capacitor as close as possible between SYS

and PGND.

17

17

BAT

SYS Output Supply Storage. This pin places the rechargeable battery or super capacitor as a storage

for the SYS output supply.

18

18

BACK_UP

Optional Input Supply from the Backup Primary Battery Cell.