数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ADP5091ACPZ-1-R7 数据表(PDF) 20 Page - Analog Devices

部件名 ADP5091ACPZ-1-R7
功能描述  Ultralow Power Energy Harvester PMUs with MPPT and Charge Management
PDF  28 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5091ACPZ-1-R7 数据表(HTML) 20 Page - Analog Devices

Back Button ADP5091ACPZ-1-R7 Datasheet HTML 16Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 17Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 18Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 19Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 20Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 21Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 22Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 23Page - Analog Devices ADP5091ACPZ-1-R7 Datasheet HTML 24Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 20 / 28 page
background image
ADP5091/ADP5092
Data Sheet
Rev. A | Page 20 of 28
POWER GOOD (PGOOD)
The ADP5091/ADP5092 allow users to set a programmable
PGOOD voltage threshold, which indicates that the SYS voltage
is at an acceptable level. It must be set by using external resistors.
Figure 42 shows the VSETPG falling threshold voltage given by
Equation 11.
+
+
=
HYST
PG
PG2
PG1
REF
INT
FALLING
SETPG
R
R
R
V
V
_
_
_
1
(11)
The SETHYST pin can program the hysteresis with an external
resistor (RPG_HYST) given by Equation 12.
+
+
=
PG2
HYST
PG
PG1
REF
INT
RISING
SETPG
R
R
R
V
V
_
_
_
1
(12)
Considering the quiescent current consumption, the sum of the
resistors that comprise the power-good resistor divider
(RPG_HYST, RPG1, and RPG2) must be more than 6 MΩ, that is,
RPG_HYST + RPG1 + RPG2 ≥ 6 MΩ
The logic high level on PGOOD is equal to the SYS voltage and
the logic low level is ground. The logic high level has approximately
11.6 kΩ (typical) internally in series to limit the available current.
The VSETPG_FALLING threshold must be greater than the VSETSD
threshold.
For the best operation of the system, use PGOOD to enable the
system load or to turn on an ultralow power load switch or to
drive an external positive channel field effect transistor (PFET)
between SYS and the system load via an inverter to determine
when the system load can be connected or removed (see Figure 48).
Table 8 shows programming threshold resistor examples
corresponding to various voltages with a 10 MΩ resistor divider.
Figure 43 shows various threshold voltages states.
0V
COLD STARTUP
MAIN BOOST
CHARGER ON
ENABLE CHIP
CHARGING BATTERY
VSYS_TH
VSYS_CHG
VSYS_CHG_HYS
VSYS_TH
TURN ON MAIN BOOST IN
ASYNCHRONOUS MODE
VSETSD
VSETSD_HYS
MAIN BOOST IN
SYNCHRONOUS MODE
TURN ON SWITCH BETWEEN
BSTO AND BAT
VSETPG_FALLING
VSETPG_RISING
PGOOD BECOMES HIGH
VBAT_TERM_HYS
VBAT_TERM
MAIN BOOST
CHARGER OFF
MAXIMUM DEVICE
RATING VOLTAGE
TURN OFF MAIN BOOST
Figure 43. ADP5091/ADP5092 Various Threshold Voltages States (See
Equation 8 and Equation 9)
POWER PATH WORKING FLOW
Figure 44 shows the power switches structure when the backup
primary battery is used. During the cold start, when a primary
battery connects to the BACK_UP pin, the S1 switch turns on.
The primary battery with the Diode D1 forward voltage drop
can be the SYS power source.
After completing the cold start, if the BAT voltage is above the
SETBK falling threshold, the BACK_UP switches remain off.
When the BAT voltage is lower than the SETBK falling threshold,
the backup control automatically selects the high voltage terminal
as the SYS power source as long as the SYS voltage is more than
VSYS_CHG. The backup control also prevents the BACK_UP
primary battery from charging the BAT pin. Meanwhile, the BAT
offset of the comparator prevents the input source from
charging the BACK_UP primary battery. Table 9 shows the
power path of the working state.
BAT
+
+
BSTO
BACK_UP
BACK_UP_M1
D1
S1
BACK_UP_M2
SYS SWITCH
BAT_M1
BAT_M2
HS
LS
SW
SYS
GATE DRIVER
GATE
DRIVER
Figure 44. ADP5091/ADP5092 Power Switches Structure
CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION
The boost regulator and regulated output in hysteresis boost mode
in the ADP5091/ADP5092 includes current-limit protection
circuitry to limit the amount of positive current flowing through
the low-side boost switch. The boost regulator current-limit
protection circuitry is a cycle-by-cycle, three-level peak current-
limit protection with a third level of 200 mA (typical), and the
regulated output current-limit protection circuitry is 100 mA
(typical). In LDO mode, the current-limit protection is designed
to limit the current when the output load reaches 260 mA
(typical). When the output load exceeds 260 mA, the output
voltage reduces to maintain a constant current limit.
Although there is no current limit at the SYS and the BAT pins,
it is recommended to limit the system load current to lower
than 1000 mA. The total resistance of the SYS switch and the
BAT switch (1.03 Ω, typical) generates a voltage drop when the
system load sinks a large current from BAT. It is also necessary
to consider the internal resistance of the storage elements
connected to the BAT pin.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com