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6.13 Parallel Interface General Timing Requirements

MIN

MAX

UNIT

ƒclock

PCLK frequency

1.0

155.0

MHz

tp_clkper

PCLK period

50% reference points

6.45

1000

tp_clkjit

PCLK jitter

Max ƒclock

See (1)

tp_wh

PCLK pulse duration high

50% reference points

2.43

tp_wl

PCLK pulse duration low

50% reference points

2.43

tp_su

Setup time – HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid before the active edge of PCLK

50% reference points

0.9

tp_h

Hold time – HSYNC_CS, DATAEN_CMD,

PDATA(23:0) valid after the active edge of PCLK

50% reference points

0.9

Transition time – all signals

20% to 80% reference

points (rising signal)

80% to 20% reference

points (falling signal)

0.2

2.0

tsetup, 3DR

This is the setup time with respect to VSYNC(2)

50% reference points

1.0

thold, 3DR

This is the hold time with respect VSYNC(3)

50% reference points

1.0

(1)

Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒclock – 5.76 ns]. Setup and hold times must be met even with clock jitter.

(2)

In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes.

(3)

In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes.

PCLK

tp_su

tp_h

tp_wh

tp_wl

tp_clkper

Figure 6-8. Parallel Interface Pixel Timing

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