ADP1606/ADP1607

Data Sheet

Rev. D | Page 10 of 16

THEORY OF OPERATION

SW

+

+

VIN

N

RESET

AGND

GND

1

L1

A

5

2

4

EN

S

R

QP

QN

RP

SW

P

6

OFF

ON

AUTO

PWM

3

FB

R1

R2

PFM

COMPARATOR

PWM

COMPARATOR

CURRENT-LIMIT

COMPARATOR

TSD

COMPARATOR

PFM

CONTROL

SHUTDOWN

ZERO

CROSS

PMOS

BULK

CONTROL

P DRIVER

CURRENT

SENSING

N DRIVER

OSCILLATOR

SOFT

START

ERROR

AMPLIFIER

BULK

CONTROL

ADJUSTABLE

MODE

THRESHOLD

DETECT

3

R1

R2

Figure 28. Block Diagram

OVERVIEW

The ADP1606/ADP1607 are current mode, synchronous, step-up

dc-to-dc switching converters available in a 1.8 V fixed output

voltage option and a 1.8 V and 3.3 V adjustable output voltage

option. Other features include logic controlled enable, fixed

PWM and light load PFM mode options, true output isolation,

internal soft start, internal fixed current limit, internal

compensation, and TSD protection.

ENABLE/SHUTDOWN

The EN input turns the ADP1606/ADP1607 on or off. Connect

EN to GND or logic low to shut down the device and reduce the

current consumption to 0.06 μA (typical). Connect EN to VIN

leave this pin floating.

MODES OF OPERATION

The ADP1606/ADP1607 are available in a fixed PWM mode

option for noise sensitive applications or in an auto PFM-to-PWM

transitioning mode option to optimize power at light loads. The

ADP1606 has a MODE pin for application controlled selection

of fixed PWM mode or automatic switching from PFM to

PWM.

Table 6. ADP1606/ADP1607 Options

Model No.

Output

Voltage

Operating

Modes

ADP1606ACPZN1.8-R7

1.8 V

MODE pin

ADP1607ACPZN001-R7

Adjustable

Fixed PWM

ADP1607ACPZN-R7

Adjustable

Fixed auto

PWM Mode

The PWM version of the ADP1607 and the PWM mode of the

ADP1606 use a current mode PWM control scheme to force

the device to maintain a fixed 2 MHz fixed frequency while

regulating the output voltage over all load conditions. The auto

mode version of the ADP1607 and the auto mode of the

ADP1606 operate in PWM for higher load currents. In PWM,

the output voltage is monitored at the FB pin through the

external resistive voltage divider. The voltage at FB is compared

to the internal 1.259 V reference by the internal error amplifier.