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ADP5076ACBZ-R7 数据表(PDF) 15 Page - Analog Devices

部件名 ADP5076ACBZ-R7
功能描述  2 A/1.2 A DC-to-DC Switching Regulator with Independent Positive and Negative Outputs
PDF  23 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADP5076ACBZ-R7 数据表(HTML) 15 Page - Analog Devices

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Data Sheet
ADP5076
Rev. A | Page 15 of 23
VIN
VPOS
TIME
VNEG
SIMULTANEOUS ENABLE MODE
(SEQ = HIGH, EN2 = HIGH)
Figure 41. Simultaneous Enable Mode
To configure the sequential enable mode, pull the SEQ pin low.
In this mode, either VPOS or VNEG can be enabled first by using
the respective EN1 pin or EN2 pin. Keep the other pin low. The
secondary supply is enabled when the primary supply completes
soft start and its feedback voltage reaches approximately 85% of
the target value. The sequential enable mode timing is shown in
Figure 42.
TIME
TIME
VPOS
VNEG
VPOS
VNEG
1. VPOS FOLLOWED BY VNEG
(SEQ = LOW, EN1 = HIGH, EN2 = LOW)
2. VNEG FOLLOWED BY VPOS
(SEQ = LOW, EN2 = HIGH, EN1 = LOW)
VIN
VIN
Figure 42. Sequential Enable Mode



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