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AS5045-ASST 数据表(PDF) 11 Page - ams AG |
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AS5045-ASST 数据表(HTML) 11 Page - ams AG |
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11 / 47 page ![]() ams Datasheet Page 11 [v2-01] 2017-Jul-13 Document Feedback AS5045 − Timing Characteristics Figure 10: Timing Characteristics Symbol Parameter Conditions Min Typ Max Units Synchronous Serial Interface (SSI) tDO active Data output activated (logic high) Time between falling edge of CSn and data output activated 100 ns tCLK FE First data shifted to output register Time between falling edge of CSn and first falling edge of CLK 500 ns TCLK / 2 Start of data output Rising edge of CLK shifts out one bit at a time 500 ns tDO valid Data output valid Time between rising edge of CLK and data output valid 357 375 394 ns tDO tristate Data output tristate After the last bit DO changes back to “tristate” 100 ns tCSn Pulse width of CSn CSn = high; To initiate read-out of next angular position 500 ns fCLK Read-out frequency Clock frequency to read out serial data >0 1 MHz Pulse Width Modulation Output fPWM PWM frequency Signal period = 4097μs ±5% at TAMB = 25°C 232 244 256 Hz Signal period = 4097μs ±10% at TAMB = -40 to 125°C 220 244 268 PWMIN Minimum pulse width Position 0d; Angle 0° 0.95 1 1.05 μs PWMAX Maximum pulse width Position 4095d; Angle 359.91° 3891 4096 4301 μs Timing Characteristics |
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