EDBA164B4PT-1DATF-R datasheet(56/152 Pages) MICRON

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• The 4-bit prefetch architecture enables BST command assertion on even clock cycles

following a WRITE or READ command. The effective burst length of a READ or WRITE

command truncated by a BST command is thus an integer multiple of four.

Figure 32: Burst WRITE Truncated by BST – WL = 1, BL = 16

Bank m

col addr a

Col addr a

WRITE

NOP

CK_c

CK_t

CA[9:0]

CMD

DQS_c

DQS_t

WL = 1

Transitioning data

BST prohibited

NOP

BST

NOP

WL × tCK + tDQSS

NOP

IN A4

IN A5

IN A6

IN A7

IN A0

IN A1

IN A2

IN A3

NOP

Notes:

1. The BST command truncates an ongoing WRITE burst WL × tCK + tDQSS after the rising

edge of the clock where the BST command is issued.

2. BST can only be issued an even number of clock cycles after the WRITE command.

3. Additional BST commands are not supported after T4 and must not be issued until after

the next READ or WRITE command.

216-Ball and 220-Ball, Dual-Channel LPDDR2 SDRAM

BURST TERMINATE Command

09005aef85eb530a

216b_220b_2ch_2e0e_embedded_lpddr2.pdf – Rev. F 08 /16 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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