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STMIPID02 数据表(PDF) 13 Page - STMicroelectronics

部件名 STMIPID02
功能描述  Dual mode MIPI CSI-2 / SMIA CCP2 de-serializer
PDF  50 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STMIPID02 数据表(HTML) 13 Page - STMicroelectronics

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8.2
User modes
8.2.1
Standard modes
The output parallel interface outputs12 bits of data, HSYNC, VSYNC, and PCLK. It is recommended to enable the
compensation macro (controlled by Mode_Reg3[5], at address 0x36) for both Standard and Bypass modes.
CSI2/CSI2
•
Main camera: CSI2 up to 1.6 Gbps (with limitation detailed in Section 8.3 CSI2 limitations)
•
Second camera: CSI2 up to 800 Mbps
CSI2/CCP2
•
Main camera: CSI2 up to 1.6 Gbps (with limitation detailed in Section 8.3 CSI2 limitations)
•
Second camera: CCP2 up to 650 Mbps
CSI2/ITU-R601
•
Main camera: CSI2 up to 1.6 Gbps (with limitation detailed in Section 8.3 CSI2 limitations)
•
Second camera: YUV directly connected to baseband parallel interface
8.2.2
Bypass modes
Bypass mode is used for any activities or applications where only PHY is needed, example, 8-bit data.
CSI2/CSI2
•
Main camera: CSI2 up to 1.6 Gbps (with limitation detailed in Section 8.3 CSI2 limitations)
•
Second camera: CSI2 up to 800 Mbps
CSI2/ ITU-R601
•
Main camera: CSI2 up to 1.6 Gbps (with limitation detailed in Section 8.3 CSI2 limitations)
•
Second camera: YUV directly connected to baseband parallel interface
8.3
CSI2 limitations
The bandwidth is limited to 800 Mbps in RAW6/RAW7 dual lane inputs. This is irrespective of the compression
used or not
STMIPID02
User modes
DS12803 - Rev 1
page 13/50



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