ADM7155

Data Sheet

Rev. C | Page 14 of 24

THEORY OF OPERATION

The ADM7155 is an ultralow noise, high power supply rejection

ratio (PSRR) linear regulator targeting radio frequency (RF)

applications. The input voltage range is 2.3 V to 5.5 V, and it can

deliver up to 600 mA of load current. Typical shutdown current

consumption is 0.2 μA at room temperature.

Optimized for use with 10 μF ceramic capacitors, the ADM7155

provides excellent transient performance.

VREG

GND

VOUT

VIN

EN

REF

REF_SENSE

1.2V REFERENCE

SHUTDOWN

ACTIVE RIPPLE

FILTER

CURRENT-LIMIT,

THERMAL

PROTECT

OTA

BYP

Figure 42. Simplified Internal Block Diagram

Internally, the ADM7155 consists of a reference, an error

amplifier, and a P-channel MOSFET pass transistor. Output

current is delivered via the PMOS pass device, which is

controlled by the error amplifier. The error amplifier compares

the reference voltage with the feedback voltage from the output

and amplifies the difference. If the feedback voltage is lower

than the reference voltage, the gate of the PMOS device is

pulled lower, allowing more current to pass and increasing the

output voltage. If the feedback voltage is higher than the

reference voltage, the gate of the PMOS device is pulled higher,

allowing less current to pass and decreasing the output voltage.

By heavily filtering the reference voltage, the ADM7155 is able

to achieve 1.5 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output

noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7155 architecture uses an internal active ripple filter. This

stage isolates the low output noise LDO from noise on the VIN

pin. The result is that the PSRR of the ADM7155 is significantly

higher over a wider frequency range than any single stage LDO.

The ADM7155 output voltage can be adjusted between 1.2 V

and 3.4 V and is available in four models that optimize the

input voltage and output voltage ranges to keep power

dissipation as low as possible without compromising PSRR

performance. The output voltage is determined by an external

voltage divider according to the following equation:

VOUT

REF

REF_SENSE

GND

VIN

EN

BYP

VREG

ADM7155-04

10µF

1µF

1µF

1kΩ < R2 < 200kΩ

10µF

10µF

OFF

ON

R1

R2

Figure 43. Typical Adjustable Output Voltage Application Schematic

The R2 value must be greater than 1 kΩ to prevent excessive

loading of the reference voltage appearing on the REF pin. To

minimize errors in the output voltage caused by the REF_SENSE

pin input current, the R2 value must be less than 200 kΩ. For

example, when R1 and R2 each equal 200 kΩ, the output

voltage is 2.4 V. The output voltage error introduced by the

REF_SENSE pin input current is 10 mV or 0.33%, assuming a

125°C.

The ADM7155 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high,

VOUT turns on, and when EN is low, VOUT turns off. For

automatic startup, tie EN to VIN.

VREG

VIN

REF_SENSE

REF

VOUT

BYP

GND

EN

7V

4V

4V

4V

4V

4V

4V

4V

4V

7V

7V

Figure 44. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 44).