ADM7155ARDZ-02-R7 datasheet(15/24 Pages) AD

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Data Sheet

ADM7155

Rev. C | Page 15 of 24

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADM7155 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance within minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and device count,

taking into consideration the operating conditions and

limitations of the IC and all real external components. For more

information about, and to obtain ADIsimPower design tools,

visit www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Multilayer ceramic capacitors (MLCCs) combine small size, low

ESR, low ESL, and wide operating temperature range, making

them an ideal choice for bypass capacitors. They are not without

faults, however. Depending on the dielectric material, the

capacitance can vary dramatically with temperature, dc bias,

and ac signal level. Therefore, selecting the proper capacitor

results in the best circuit performance.

Output Capacitor

The ADM7155 is designed for operation with ceramic

capacitors but functions with most commonly used capacitors

when care is taken with regard to the effective series resistance

(ESR) value. The ESR of the output capacitor affects the stability

of the LDO control loop. A minimum of 10 μF capacitance with

an ESR of 0.2 Ω or less is recommended to ensure the stability

of the ADM7155. Output capacitance also affects transient

response to changes in load current. Using a larger value of

output capacitance improves the transient response of the

ADM7155 to large changes in load current. Figure 45 shows the

transient responses for an output capacitance value of 10 μF.

CH1 200mA Ω BW

M4µs

A CH1

212mA

T 10.2%

CH2 5mV

Figure 45. Output Transient Response, VOUT = 3.3 V, COUT = 10 μF,

CH1 = Load Current, CH2 = VOUT

Input and VREG Capacitor

Connecting a 10 μF capacitor from VIN to GND reduces the

circuit sensitivity to PCB layout, especially when long input

traces or high source impedance are encountered.

To maintain the best possible stability and PSRR performance,

connect a 10 μF capacitor from VREG to GND. When more

than 10 μF of output capacitance is required, increase the input

and the VREG capacitors, CREG, to match it.

REF Capacitor

The REF capacitor, CREF, is necessary to stabilize the reference

amplifier. Connect at least a 1 μF capacitor between REF and GND.

BYP Capacitor

The BYP capacitor, CBYP, is necessary to filter the reference

buffer. A 1 μF capacitor is typically connected between BYP and

GND. Capacitors as small as 0.1 μF can be used; however, the

output noise voltage of the LDO increases as a result.

In addition, the BYP capacitor value can be increased to reduce

the noise below 1 kHz at the expense of increasing the start-up

time of the LDO. Very large values of CBYP significantly reduce

the noise below 10 Hz. Tantalum capacitors are recommended

for capacitors larger than approximately 33 μF because solid

tantalum capacitors are less prone to microphonic noise issues.

A 1 μF ceramic capacitor in parallel with the larger tantalum

capacitor is recommended to ensure good noise performance at

higher frequencies.

CBYP (µF)

1000

100

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

10Hz TO 100kHz

100Hz TO 100kHz

Figure 46. RMS Noise vs. CBYP

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