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ADIN2111BCPZ-R7 数据表(PDF) 34 Page - Analog Devices |
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ADIN2111BCPZ-R7 数据表(HTML) 34 Page - Analog Devices |
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34 / 125 page  Data Sheet ADIN2111 APPLICATIONS INFORMATION analog.com Rev. 0 | 34 of 125 External Clock Input If using a single-ended reference clock on XTAL_I/CLK_IN, leave XTAL_O open circuit. This clock must be an ac-coupled 0.8 V p-p to 2.5 V p-p sine or (filtered) square wave signal. In Figure 20, VS p-p is the peak-to-peak voltage of the clock source. C1 is the series capacitor from the clock source to XTAL_I/CLK_IN. C2 is the capacitor from XTAL_I/CLK_IN to ground. If VS p-p < 2.5 V p-p, ► C2 is not required ► C1 = 1 nF If VS p-p ≥ 2.5 V p-p, ► C2 = 10 pF ► C1 = 2.5 (13 pF + CPCBx)/(VS p-p – 2.5) ADIN2111 C1 C2 VS p-p SIGNAL SWING < 2.5V p-p Figure 20. External Clock Connection |
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