Data Sheet

ADRF5345

THEORY OF OPERATION

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Rev. 0 | 9 of 11

The ADRF5345 integrates a NVG and requires a single, positive

supply voltage applied to the VDD pin. Bypass capacitors are

recommended on the supply and control lines to minimize RF

coupling.

All of the RF ports (RFC and RF1 to RF4) are dc-coupled to 0 V,

and no dc blocking is required at the RF ports when the RF line

potential is equal to 0 V. The RF ports are internally matched to

50 Ω. Therefore, external matching networks are not required.

The ADRF5345 integrates a driver to perform logic functions inter-

nally and to provide the user with the advantage of a simplified

LVCMOS-/LVTTL-compatible control interface. The driver features

three digital control input pins (LS, V1, and V2) that control the state

of the RFx paths. See Table 6.

The logic select (LS) input allows the user to define the control input

logic sequence for the RF path selections. The logic levels applied

to the V1 and V2 pins determine which RFx port is in the insertion

loss state while the other three paths are in the isolation state.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The switch design is

bidirectional with equal power handling. The RF input signal can be

applied to the RFC port or the selected RF throw port. The isolation

paths provide high loss between the insertion loss path and the

unselected RF throw ports.

The ideal power-up sequence is as follows:

1. Connect GND.

2. Power up VDD.

3. Apply the digital control inputs: LS, V1, and V2. Applying digital

control inputs before the VDD supply can inadvertently forward

bias and damage the internal ESD protection structures. A

series 1 kΩ resistor can be used to limit the current flowing

into the control pin in such cases. If the control pins are not

driven to a valid logic state (that is, controller output is in high

impedance state) after VDD is powered up, it is recommended

to use pull-up and power-down resistors.

4. Apply an RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

Table 6. Control Voltage Truth Table

Digital Control Inputs

RFx Paths

LS

V1

V2

RF1 to RFC

RF2 to RFC

RF3 to RFC

RF4 to RFC

Low

Low

Low

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)

Low

High

Low

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

Low

Low

High

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

Low

High

High

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

High

Low

Low

Isolation (off)

Isolation (off)

Isolation (off)

Insertion loss (on)

High

High

Low

Isolation (off)

Isolation (off)

Insertion loss (on)

Isolation (off)

High

Low

High

Isolation (off)

Insertion loss (on)

Isolation (off)

Isolation (off)

High

High

High

Insertion loss (on)

Isolation (off)

Isolation (off)

Isolation (off)