Preliminary Technical Data

ADCMP580/ADCMP581/ADCMP582

Rev. PrA | Page 12 of 16

TYPICAL APPLICATION CIRCUITS

Q

ADCMP580

Q

LATCH

INPUTS

50

Ω

50

Ω

GND

Figure 20. Zero-Crossing Detector with CML Outputs

LATCH

INPUTS

GND

75

Ω

75

Ω

50

Ω

50

Ω

100

Ω

100

Ω

ADCMP580

Figure 21. Interfacing CML to a 50 Ω Ground-Terminated Instrument

Q

50

Ω

50

Ω

Q

LATCH

INPUTS

GND

ADCMP580

Figure 22. LVDS to a 50 Ω Back-Terminated (RS)ECL Receiver

ADCMP580

50

Ω

1.5k

Ω

50

Ω

Figure 23. Disabling the Latch Feature

50

Ω

50

Ω

+

–

Q

Q

LATCH

INPUTS

GND

ADCMP580

Figure 24. Comparator with –2 V to +3 V Input Range

HYS

50

Ω

50

Ω

ADCMP580

0

Ω TO 5kΩ

Figure 25. Adding Hysteresis Using the HYS Control