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MCIMX503CVM8B 数据表(PDF) 90 Page - NXP Semiconductors |
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MCIMX503CVM8B 数据表(HTML) 90 Page - NXP Semiconductors |
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90 / 136 page  i.MX50 Applications Processors for Consumer Products, Rev. 7 Electrical Characteristics Freescale Semiconductor 90 4.9.9.1 SSI Transmitter Timing with Internal Clock Figure 51 depicts the SSI transmitter internal clock timing and Table 66 lists the timing parameters for the SSI transmitter internal clock. . Figure 51. SSI Transmitter Internal Clock Timing Diagram Table 66. SSI Transmitter Timing with Internal Clock ID Parameter Min Max Unit Internal Clock Operation SS1 (Tx/Rx) CK clock period 81.4 — ns SS2 (Tx/Rx) CK clock high period 36.0 — ns SS3 (Tx/Rx) CK clock rise time — 6.0 ns SS4 (Tx/Rx) CK clock low period 36.0 — ns SS5 (Tx/Rx) CK clock fall time — 6.0 ns SS6 (Tx) CK high to FS (bl) high — 15.0 ns SS8 (Tx) CK high to FS (bl) low — 15.0 ns SS10 (Tx) CK high to FS (wl) high — 15.0 ns SS12 (Tx) CK high to FS (wl) low — 15.0 ns SS14 (Tx/Rx) Internal FS rise time — 6.0 ns SS15 (Tx/Rx) Internal FS fall time — 6.0 ns SS16 (Tx) CK high to STXD valid from high impedance — 15.0 ns SS19 SS1 SS2 SS4 SS3 SS5 SS6 SS8 SS10 SS12 SS14 SS18 SS15 SS17 SS16 SS43 SS42 Note: SRXD input in synchronous mode only TXC (Output) TXFS (wl) (Output) TXFS (bl) (Output) RXD (Input) TXD (Output) |
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