MXC62320MP datasheet(7/8 Pages) MEMSIC

7 / 8 page

MEMSIC MXC6232xG/H/M/N Rev.A

Page 7 of 8

4/11/2010

defined by a HIGH to LOW transition on the SDA line

while SCL line is HIGH. A “STOP” condition is defined by

a LOW to HIGH transition on the SDA line while SCL line

is HIGH. All data transfer in I2C system is 8-bits long. Each

byte has to be followed by an acknowledge bit. Each data

transfer involves a total of 9 clock cycles. Data is

transferred starting with the most significant bit (MSB).

After a “START” condition, master device calls a specific

slave device, in our case, the Memsic accelerometer with a

7-bit device address. To avoid potential address conflict,

either by ICs from other manufacturers or by other Memsic

accelerometers on the same bus, a total of 8 different

addresses can be programmed into a Memsic device at the

factory.

Following the 7-bit address, the 8th bit determines the

direction of data transfer: [1] for READ and [0] for

WRITE. After being addressed, the available Memsic

device being called will respond by an “Acknowledge”

signal, which is pulling SDA line LOW.

In order to read an acceleration signal, the master device

should operate a WRITE action with a code of [xxxxxxx0]

into the Memsic device 8-bit internal register.

Bit Name

Function

PD (Power Down)

Power down [1]/on [0]

ST (Self-test)

Self-test on [1]/off [0]

BGTST (bandgap test)

Bandgap test [1]/normal[0]

TOEN

(temperature

out enable)

Temp Out EN [1]/disable[0]

The ST bit serves as a self-test function to verify the

Memsic accelerometer is operating properly. BGTST is

used to calibrate the temperature output signal’s initial

offset. By flipping the BGTST bit and taking the average of

two readings, the temperature output initial offset will be

calibrated to within datasheet specifications.

After writing code of [xxxxxxx0] into the control register,

if a “READ” signal is received, during next 9 clock cycles,

the Memsic device being called will transfer 8-bits of data

to the I2C bus. If an “Acknowledge” by master device is

received, the Memsic device will continue to transfer the

next byte. The same procedure repeats until 5 bytes of data

are transferred to master device. Those 5 bytes of data are

defined as following (“T” is temperature output):

1. Internal register

2. MSB X/T axis

3. LSB X/T axis

4. MSB Y axis

5. LSB Y axis

Even though each axis consists of two bytes, which are 16-

bits of data, the actual accelerometer resolution is limited to

either 12 bits or 10 bits, which depends on an internal

output register refresh rate. Unused MSB’s will be simply

filled by “0”s.

Note that temperature output shares the same registers with

X channel output. Customer can select which signal needs

to be read out by using TOEN bit.

Resolution

10 bits

12 bits

Refreshing rate

400Hz

100Hz

Zero-G Offset

512

2048

Note: 20mS (MXC6232xG/M) and 5mS (MXC6232xHN)

typical waiting time is necessary between each data

acquisition.

The master can stop slave data transfer after any of the five

bytes by not sending an acknowledge command and

followed by a “STOP” condition.

POWER DOWN MODE

The Memsic accelerometer can enter a power down mode

by the master device writing a code of [xxxxxxx1] into the

accelerometer’s internal register. A wake up operation is

performed when the master writes into the same register a

code of [xxxxxxx0]. Note that the MXC6232xG/H/M/N

needs about 75mS (typical) for power up time.

EXAMPLE OF DATA COMMUNICATION

First cycle: START followed by a calling to slave address

[0010xxx] to WRITE (8th SCL, SDA keep low). [xxx] Is

determined by factory programming, a total of 8 different

addresses are available.

Second cycle: After an acknowledge signal is received by

the master device (Memsic device pulls SDA line low

during 9th SCL pulse), master device sends “[00000000]” as

the target address to be written into. Memsic device should

acknowledge at the end (9th SCL pulse). Note: since

Memsic device has only one internal register that can be

written into, user should always indicate “[00000000]” as

the write address.

Third cycle: Master device writes to internal Memsic device

memory code “[xxxxxxx0]” as a wake-up call. The Memsic

device should send acknowledge signal. A STOP command

indicates the end of write operation. A 75msS (typical) wait

period should be given to Memsic device to return from a

power-down mode. The delay value depends on the type of

Memsic device. Generally speaking, low power products

tend to have longer startup time.

Fourth cycle: Master device sends a START command

followed by calling Memsic device address with a WRITE

(8th SCL, SDA keep low). An “acknowledge” should be

sent by Memsic device at the end.

Fifth cycle: Master device writes to Memsic device a

“[00000000]” as the starting address for which internal

memory is to be read. Since “[00000000]” is the address of

internal control register, reading from this address can serve

as a verification of operation and to confirm the write

command has been successful. Note: the starting address in

principle can be any of the 5 addresses. For example, user

can start read from address [0000001], which is X channel

MSB.

MXC62320MP 数据表(PDF) 7 Page - MEMSIC Semiconductor (Tianjin) Co., Ltd.

MXC62320MP 数据表(HTML) 7 Page - MEMSIC Semiconductor (Tianjin) Co., Ltd.

Html Pages

1 2 3 4 5 6 7 8

数据表下载