AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
AL4CS211/AL4CS221/AL4CS231/AL4CS241/AL4CS251
December 14, 2001
7
7.0 Pin Definition and Description
The pin-out definition and function are described as following:
Write Bus Signals
Pin
Symbol
Pin name
TQFP
Pin no.
PLCC
Pin no.
I/O
Typ
Description
D[8:0]
Data Inputs
[26:32], 1,
2
[30:32],
[1:6]
I
9-bit input data bus.
/WEN1
Write Enable 24
28
I
/WEN1 is the only Write Enable pin, if FIFO is
configured to support programmable flags.
When /WEN1 is LOW, data is written into the
FIFO on every rising edge of WCLK. If the
FIFO is configured to have two write enables,
/WEN1 must be LOW and WEN2 must be
HIGH to write data into the FIFO. When FIFO
is full (/FF = LOW), data will not be written
into FIFO.
WEN2
</LD>
Write Enable 22
26
I
The FIFO is configured at the Reset to either
have two write enables or support
programmable flags. If Write Enable 2<Load>
(WEN2</LD>) is HIGH at Reset (/RS =
LOW), this pin will operate as a second Write
Enable pin. If Write Enable 2<Load>
(WEN2</LD>) is LOW at Reset (/RS = LOW),
the FIFO is configured to support
programmable flags function and /WEN1 is the
only Write Enable pin.
WCLK
Write Clock 23
27
I
Data is written into the FIFO on a rising edge of
WCLK when the Write Enable(s) are asserted.
Data will not be written into FIFO if /FF is not
LOW.
Read Bus Signals
Pin
symbol
Pin name
TQFP
Pin no.
PLCC
Pin no.
I/O
typ
Description
Q[8:0]
Data Outputs [21:12]
[24:16]
O
9-bit output data bus.
/REN1
Read Enable 6
10
I
When both /REN1 and /REN2 are LOW, data is
read from the FIFO on every rising edge of
RCLK. Data will not be read from the FIFO if
the /EF is LOW.
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