ADP7185

Data Sheet

Rev. 0 | Page 16 of 19

Figure 48 shows the change in capacitance vs. the dc bias voltage

characteristics of a 0805 case, 4.7 μF, 10 V, X5R capacitor. The

capacitor size and voltage ratings strongly influence the voltage

stability of a capacitor. In general, a capacitor in a larger package

or with a higher voltage rating exhibits improved stability. The

temperature variation of the X5R dielectric is about ±15% over

the −55°C to +85°C temperature range and is not a function of

package size or voltage rating.

0

024

68

10

12

DC BIAS VOLTAGE (V dc)

5.64

4.70

1.88

2.82

3.76

0.94

Figure 48. Change in Capacitance vs. DC Bias Voltage

Use Equation 4 to determine the worst-case capacitance,

accounting for capacitor variation over temperature, component

tolerance, and voltage.

(4)

where:

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient

(TEMPCO) over −55°C to +85°C is assumed to be 15% for an

X5R dielectric. The tolerance of the capacitor (TOL) is assumed

Substituting these values in Equation 4 yields

Therefore, the capacitor chosen in this example meets the

minimum capacitance requirement of the LDO over temperature

and tolerance at the chosen output voltage.

To guarantee the performance of the ADP7185, it is imperative

to evaluate the effects of dc bias, temperature, and tolerances on

the behavior of the capacitors for each application.

UNDERVOLTAGE LOCKOUT (UVLO)

The UVLO circuitry protects the system from power supply

brownouts. If the input voltage on VIN is more positive than

the minimum −1.58 V UVLO falling threshold, the LDO output

shuts down. The LDO enables again when the voltage to VIN is

more negative than the maximum −1.77 V UVLO rising threshold.

A typical hysteresis of 90 mV within the UVLO circuitry prevents

the device from oscillating due to the noises from VIN.

0.05

0

–0.55

–1.60

VIN (V)

–1.74

–1.72

–1.70

–1.68

–1.66

–1.64

–1.62

–0.50

–0.45

–0.40

–0.35

–0.30

–0.25

–0.20

–0.15

–0.10

–0.05

Figure 49. Typical UVLO Behavior, VOUT = −0.5 V

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADP7185 is protected against damage due to excessive

power dissipation by current-limit and thermal overload

protection circuits. The ADP7185 is designed to reach current

limit when the output load reaches −900 mA (typical). When

the output load exceeds −900 mA, the output voltage is reduced

to maintain a constant current limit.

Thermal overload protection is included, which limits the

junction temperature to a maximum of 150°C (typical). Under

extreme conditions (that is, high ambient temperature and

power dissipation) when the junction temperature begins to rise

above 150°C, the output is turned off, reducing the output

current to zero. When the junction temperature drops below

135°C (typical), the output is turned on again, and the output

current is restored to its nominal value.

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADP7185 reaches current limit so that only −900 mA

is conducted into the short. If self-heating of the junction becomes

great enough to cause its temperature to rise above 150°C, thermal

shutdown activates, turning off the output and reducing the

output current to zero. As the junction temperature cools and

drops below 135°C, the output turns on and conducts −900 mA

into the short, again causing the junction temperature to rise

above 150°C. This thermal oscillation between 135°C and

150°C causes a current oscillation between −900 mA and 0 A

that continues as long as the short remains at the output. Current-

limit and thermal overload protections protect the device

against accidental overload conditions. For reliable operation,

externally limit device power dissipation so that junction

temperatures do not exceed 125°C.