SY75603A datasheet(4/26 Pages) MICROCHIP

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SY75602A/02B/603A/03B/604A/04B

DS20006508B-page 4



2021 Microchip Technology Inc. and its subsidiaries

Input Leakage Current for

OExb Inputs (Includes

Current due to Pull-Down

Resistors)

IIL_OE

–5

—

µA

VIN = VDD, VIN = GND

SY75603/4 only

Single Ended Input Common

Mode Voltage (IN_p) (HCSL

Common Mode)

VSIC

0.25

—

0.55

—

Single Ended Input Voltage

Swing for IN_p

VSID

0.3

—

1.45

—

Maximum Input Voltage

VIN(MAX)

—

1.15

—

Minimum Input Voltage

VIN(MIN)

–0.3

—

Input Frequency (Differential)

fIN

—

250

MHz —

Input Frequency (Single

Ended)

fIN_SE

—

250

MHz —

Input Duty Cycle

—

Note 1: Tested with 100 MHz clock with outputs driving 5” long trace terminated with 2 pF capacitors to ground.

2: Output Enable control pins are synchronous with the input clock and it takes four rising edges before out-

puts get enabled and five rising edges before outputs get disabled. Hence the minimum input frequency is

greater than 0 Hz. Once the outputs are enabled the input clock frequency can be reduced to 0 Hz.

OUTPUT ELECTRICAL CHARACTERISTICS

Electrical Characteristics: VDD = 3.3V ±10%, 2.5V±10%; 1.8V±10%; TA = –40°C to +105°C, CLOAD = 2 pF unless

noted.

Parameter

Symbol

Min.

Typ.

Max.

Units Conditions

Rising Edge Rate

—

2.5

V/ns Note 2, Note 3

Falling Edge Rate

—

2.5

V/ns Note 2, Note 3

Differential Output High Voltage

VOH

0.6

—

0.9

Note 2

Differential Output Low Voltage

VOL

–0.9

—

–0.6

Note 2

Absolute Crossing Voltage

VCROSS

0.25

—

0.55

Note 1, Note 4,

Note 5

Variation of VCROSS Over All Rising Clock

Edges

VCROSS_DELTA

—

0.14

Note 1, Note 4,

Note 8

Ring Back Voltage Margin

VRB

–0.1

—

0.1

Note 2, Note 10

Time Before VRB is Allowed

tSTABLE

500

—

Note 2, Note 10

Cycle-to-Cycle Additive Jitter

tCCJITTER

—

6.5

8.1

Note 2

Absolute Maximum Output Voltage

VMAX

—

1.15

Note 1, Note 6

Absolute Minimum Output Voltage

VMIN

–0.3

—

Note 1, Note 7

Output Duty Cycle

VDC

When input has

50% duty cycle

and VIN ≥ 200 mV,

Note 2

Rising to Falling Edge Matching

Rise-Fall

Matching

—

Note 1, Note 11

Clock Source DC Impedance (OUTx_p) for

part with 85Ω embedded differential series

resistance (parts with suffix “A”)

ZC-DC_OUT_p

—

Note 1, Note 9

ELECTRICAL CHARACTERISTICS

Electrical Characteristics: VDD = 3.3V ±10%, 2.5V±10%; 1.8V±10%; TA = –40°C to +105°C, unless noted.

Parameter

Symbol

Min.

Typ.

Max.

Units Conditions

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