SY75602A/02B/603A/03B/604A/04B

DS20006508B-page 6

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2021 Microchip Technology Inc. and its subsidiaries

JITTER AND PHASE NOISE

Parameter

Symbol

Min. Typ. Max.

Units

Conditions

Peak-to-Peak Additive Jitter

—

—

4.5

ps

Note 1, Note 2

Additive Jitter as per PCIe 1.0

(1.5 MHz to 22 MHz)

—

0.7

0.8

Additive Jitter as per PCIe 2.0 high band (1.5 MHz

to 50 MHz)

70

90

Additive Jitter as per PCIe 2.0 low band

(10 kHz to 1.5 MHz)

—

14

20

Additive Jitter as per PCIe 2.0 mid band

(5 MHz to 16 MHz)

—

55

74

Additive Jitter as per PCIe 3.0

(PLL_BW = 2 to 5 MHz, CDR = 10 MHz)

—

18

22

Additive Jitter as per PCIe 4.0

(PLL_BW = 2 to 5 MHz, CDR = 10 MHz)

—

18

22

Additive Jitter as per PCIe 5.0

(PLL_BW = 0.5 to 1.8 MHz, CDR for 32 GT/s CC)

—

7

10

Additive jitter as per Intel QPI 9.6 Gbps

—

35

45

Additive RMS jitter in 1 MHz to 20 MHz band

—

51

66

Note 1, Note 2

(100 MHz clock)

—

40

54

Note 1, Note 2

(133 MHz clock)

Additive RMS jitter in 12 kHz to 20 MHz band

tj_12k_20M

—

52

68

Note 1, Note 2

(100 MHz clock)

—

44

58

Note 1, Note 2

(133 MHz clock)

Noise Floor

NF

— –165 –163

dBc/Hz Note 1, Note 2

(100 MHz clock)

— –165 –163

dBc/Hz Note 1, Note 2

(133 MHz clock)

Note 1: Measured into AC test load as per Figure 1-7.

2: Measured from differential crossing point to differential crossing point.

3: Measured with 50Ω termination in instrument without a test load.