Data Sheet

ADP322/ADP323

Rev. E | Page 17 of 24

APPLICATIONS INFORMATION

ADIsimPOWER DESIGN TOOL

The ADP323 is supported by the ADIsimPower design tool set.

ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic, bill of materials,

and calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and parts count,

taking into consideration the operating conditions and limitations

of the IC and all real external components. For more information

about, and to obtain ADIsimPower design tools, visit

www.analog.com/ADIsimPower.

CAPACITOR SELECTION

Output Capacitor

The ADP322/ADP323 are designed for operation with small,

space-saving ceramic capacitors, but the devices function with

most commonly used capacitors as long as care is taken with the

effective series resistance (ESR) value. The ESR of the output

capacitor affects the stability of the LDO control loop. A minimum

of 0.70 µF capacitance with an ESR of 1 Ω or less is recommended

to ensure the stability of the ADP322/ADP323.

Transient response to changes in load current is also affected by

output capacitance. Using a larger value of output capacitance

improves the transient response of the ADP322/ADP323 to large

changes in the load current. Figure 51 shows the transient

response for an output capacitance value of 1 µF.

Ω

CH2 50mV

CH4 10mV

CH3 10mV

M40µs

A CH1

44mA

1

2

3

4

B

W

B

W

B

W

B

W

Figure 51. Output Transient Response,

Input Bypass Capacitor

Connecting a 1 µF capacitor from VIN1/VIN2, VIN3, and

VBIAS to GND reduces the circuit sensitivity to the PCB layout,

especially when long input traces or high source impedance is

encountered. If an output capacitance greater than 1 µF is

required, the input capacitor can be increased to match it.

Input and Output Capacitor Properties

Any good quality ceramic capacitor can be used with the ADP322/

ADP323, as long as the capacitor meets the minimum capacit-

ance and maximum ESR requirements. Ceramic capacitors are

manufactured with a variety of dielectrics, each with a different

behavior over temperature and applied voltage. Capacitors must

have an adequate dielectric to ensure the minimum capacitance

over the necessary temperature range and dc bias conditions. X5R

or X7R dielectrics with a voltage rating of 6.3 V or 10 V are

recommended. Y5V and Z5U dielectrics are not recommended

due to their poor temperature and dc bias characteristics.

Figure 52 depicts the capacitance vs. voltage bias characteristic

of a 0402 1 µF, 10 V, X5R capacitor. The voltage stability of a

capacitor is strongly influenced by the capacitor size and voltage

rating. In general, a capacitor in a larger package or with a higher

voltage rating exhibits better stability. The temperature variation

of the X5R dielectric is about ±15% over the −40°C to +85°C

temperature range and is not a function of the package or

voltage rating.

1.2

1.0

0.8

0.6

0.4

0.2

0

0

2

4

6

8

10

VOLTAGE (V)

Figure 52. Capacitance vs. Voltage Bias Characteristic