STM32WL55JC datasheet(39/147 Pages) STMICROELECTRONICS

39 / 147 page

DS13293 Rev 2

39/147

STM32WL55/54xx

Functional overview

•

Semaphore clear protection: A semaphore is only unlocked when COREID and

PROCID match.

•

Global semaphore clear per COREID

3.15

Inter-processor communication controller (IPCC)

The IPCC is used for communicating data between two processors.

The IPCC block provides a non blocking signaling mechanism to post and retrieve

communication data in an atomic way. It provides the signaling for twelve channels:

•

six channels in the direction from processor 1 to processor 2

•

six channels in the opposite direction

It is then possible to have two different communication types in each direction.

The IPCC communication data must be located in a common memory, that is not part of the

IPCC block.

3.16

General-purpose inputs/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as

input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the

GPIO pins are shared with digital or analog alternate functions. Fast I/O toggling can be

achieved thanks to their mapping on the AHB2 bus.

The I/Os alternate function configuration can be locked if needed following a specific

sequence in order to avoid spurious writing to the I/Os registers.

3.17

Direct memory access controller (DMA)

The DMA (direct memory access) is used to provide high-speed data transfer between

peripherals and memory, as well as memory to memory. Data can be quickly moved by

DMA without any CPU actions. This keeps CPU resources free for other operations.

The DMA controller has 14 channels in total. A full cross matrix allows the peripherals, with

DMA support, to be mapped on any of the available DMA channels. Each DMA channel has

an arbiter for handling the priority between DMA requests.

The DMA main features are listed below:

•

14 independently configurable channels (requests)

•

a full cross matrix between peripherals and all 14 channels and an hardware trigger

possibility through the DMAMUX1

•

software programmable priorities between requests from channels of one DMA (four

levels: very-high, high, medium, low), plus hardware priorities management in case of

equality (example: request 1 has priority over request 2)

•

independent source and destination transfer size (byte, half-word, word), emulating

packing and unpacking. Source/destination addresses must be aligned on the data

size.

•

support for circular buffer management

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