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STM8AF6213 数据表(PDF) 57 Page - STMicroelectronics |
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STM8AF6213 数据表(HTML) 57 Page - STMicroelectronics |
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57 / 112 page ![]() DS9884 Rev 9 57/112 STM8AF6213/13A/23/23A/26 Electrical characteristics 108 Figure 9. fCPUmax versus VDD Table 28. Operating conditions at power-up/power-down Symbol Parameter Conditions Min Typ Max Unit tVDD VDD rise time rate - 2(1) 1. Guaranteed by design. - ∞ µs/V VDD fall time rate(2) 2. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the minimum operating voltage (VDD min) when the tTEMP delay has elapsed. - 2(1) - ∞ tTEMP Reset release delay VDD rising - - 1.7 ms VIT+ Power-on reset threshold(3) 3. There is inrush current into VDD present after device power on to charge CEXT capacitor. This inrush energy depends from CEXT capacitor value. For example, a CEXT of 1μF requires Q=1 μF x 1.8V = 1.8 μC. - 2.6(1) 2.7 2.85 V VIT- Brown-out reset threshold - 2.5 2.65 2.8(1) VHYS(BOR) Brown-out reset hysteresis -- 70(1) -mV MSv37798V1 16 12 8 4 0 3.0 4.0 5.0 5.5 Functionality guaranteed @TA -40 to 150 °C Supply voltage (V) Functionality not guaranteed in this area fCPU (MHz) 24 |
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