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TLV9152SIRUGR 数据表(PDF) 6 Page - Texas Instruments |
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TLV9152SIRUGR 数据表(HTML) 6 Page - Texas Instruments |
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6 / 77 page ![]() 1 OUT1 8 V+ 2 IN1± 7 OUT2 3 IN1+ 6 IN2± 4 V± 5 IN2+ Not to scale Figure 5-4. TLV9152 D, DDF, DGK, and PW Package 8-Pin SOIC, SOT-23, TSSOP, and VSSOP (Top View) 1 OUT1 8 V+ 2 IN1± 7 OUT2 3 IN1+ 6 IN2± 4 V± 5 IN2+ Not to scale Thermal Pad A. Connect thermal pad to V–. See Packages with and Exposed Thermal Pad for more information. Figure 5-5. TLV9152 DSG Package(A) 8-Pin WSON With Exposed Thermal Pad (Top View) Table 5-3. Pin Functions: TLV9152 PIN I/O DESCRIPTION NAME NO. +IN A 3 I Noninverting input, channel A +IN B 5 I Noninverting input, channel B –IN A 2 I Inverting input, channel A –IN B 6 I Inverting input, channel B OUT A 1 O Output, channel A OUT B 7 O Output, channel B V+ 8 — Positive (highest) power supply V– 4 — Negative (lowest) power supply TLV9151, TLV9152, TLV9154 SBOS986E – OCTOBER 2019 – REVISED JANUARY 2022 www.ti.com 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TLV9151 TLV9152 TLV9154 |
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