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ST25R95 数据表(PDF) 3 Page - STMicroelectronics |
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ST25R95 数据表(HTML) 3 Page - STMicroelectronics |
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3 / 61 page ![]() 1.2 Clock management The ST25R95 incorporates two clock sources, a high frequency oscillator (HFO) and a low frequency oscillator (LFO). The HFO uses an external 27.12 MHz crystal to generate the internal system clock and the clock for the drivers to generate the RF field. The LFO uses an internal 32 kHz RC oscillator to generate a slow system clock for low power operation modes. In card emulation mode, a built-in clock recovery block is available which recovers the clock from the external HF field. This block can be selected instead of HFO by setting the ClkRec bit in the Protocol Select command. 1.3 Power supply The ST25R95 has two power supply pins: • VPS: supply of digital and analog blocks • VPS_TX: direct supply of the driver stage 1.4 List of terms Table 1. List of terms Term Meaning AFE Analog front end DAC Digital analog converter FDT Frame delay time FWT Frame waiting time GND Ground HFO High frequency oscillator LFO Low frequency oscillator MCU Microcontroller unit MIFARE (1) Communication protocol NFC Near field communication RFID Radio frequency identification RFU Reserved for future use RWT Response waiting time SPI Serial peripheral interface tL Low frequency period tREF Reference time WFE Wait for event 1. MIFARE® and MIFARE® Classic are registered trademarks of NXP BV. ST25R95 Clock management DS12807 - Rev 4 page 3/61 |
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