AD5535

Preliminary Technical Data

Rev. PrE | Page 12 of 16

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5535*

ADSP-2101/

ADSP-2103*

SCLK

SYNC

SCLK

DT

TFS

Figure 11. AD5535 to ADSP-2101/ADSP-2103 Interface

AD5535 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is

configured for master mode (MSTR = 1), clock polarity bit

(CPOL) = 0, and clock phase bit (CPHA) = 1. The SPI is

configured by writing to the SPI control register (SPCR)—see

the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK

of the AD5535 and the MOSI output drives the serial data line

(DIN) of the AD5535. The SYNC signal is derived from a port

line (PC7). When data is being transmitted to the AD5535, the

SYNC line is taken low (PC7).

Data appearing on the MOSI output is valid on the falling edge

of SCK. The 68HC11 transfers only eight bits of data during

each serial transfer operation; therefore, three consecutive write

operations are necessary to transmit 19 bits of data. Data is

transmitted MSB first. It is important to left-justify the data in

the SPDR register so that the first 19 bits transmitted contain

valid data. PC7 must be pulled low to start a transfer. It is taken

high and pulled low again before any further write cycles can

take place. See Figure 12.

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5535*

MC68HC11*

SCLK

SYNC

SCK

MOSI

PC7

Figure 12. AD5535 to MC68HC11 Interface

AD5535 to PIC16C6X/7X

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit = 0. This is done by

writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In

this example, I/O port RA1 is being used to pulse SYNC and

enable the serial port of the AD5535. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive write operations are

necessary to transmit 19 bits of data. Data is transmitted MSB

first. It is important to left-justify the data in the SPDR register

so that the first 19 bits transmitted contain valid data. RA1 must

be pulled low to start a transfer. It is taken high and pulled low

again before any further write cycles can take place. Figure 13

shows the connection diagram.

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5535*

PIC16C6x/7x*

SCLK

SYNC

SCK/RC3

SDI/RC4

RA1

Figure 13. AD5535 to PIC16C6x/7x Interface

AD5535 to 8051

The AD5535 requires a clock synchronized to the serial data.

The 8051 serial interface must, therefore, be operated in

Mode 0. In this mode, serial data exits the 8051 through RxD,

and a shift clock is output on TxD. The SYNC signal is derived

from a port line (P1.1). Figure 14 shows how the 8051 is

connected to the AD5535. Because the AD5535 shifts data out

on the rising edge of the shift clock and latches data in on the

falling edge, the shift clock must be inverted. Note also that the

AD5535 requires its data with the MSB first. Because the 8051

outputs the LSB first, the transmit routine must take this into

account.

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5535*

8051*

SCLK

SYNC

TxD

RxD

P1.1

Figure 14. AD5535 to 8051 Interface