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MIMXRT685SFVKB 数据表(PDF) 78 Page - NXP Semiconductors

部件名 MIMXRT685SFVKB
功能描述  Dual-core microcontroller with 32-bit Cortex짰-M33 and Xtensa HiFi4 Audio DSP CPUs
PDF  165 Pages
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制造商  NXP [NXP Semiconductors]
网页  http://www.nxp.com
标志 NXP - NXP Semiconductors

MIMXRT685SFVKB 数据表(HTML) 78 Page - NXP Semiconductors

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RT600
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors B.V. 2021. All rights reserved.
Product data sheet
Rev. 1.9 — 30 December 2021
78 of 163
NXP Semiconductors
RT600
Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4
Audio DSP CPUs
• Activity on the SPI in slave mode allows wake-up from deep-sleep mode on any
enabled interrupt.
Remark: Texas Instruments SSI and National Microwire modes are not supported.
10.17.4.3 I2C-bus interface
The I2C-bus is bidirectional for inter-IC control using only two wires: a serial clock line
(SCL) and a serial data line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (for example, an LCD driver) or a transmitter
with the capability to both receive and send information (such as memory). Transmitters
and/or receivers can operate in either master or slave mode, depending on whether the
chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus and
can be controlled by more than one bus master connected to it.
Features
• All I2Cs support standard, Fast-mode, and Fast-mode Plus with data rates of up to
1Mbit/s.
• All I2Cs support high-speed slave mode with data rates of up to 3.4 Mbit/s.
• Independent Master, Slave, and Monitor functions.
• Supports both Multi-master and Multi-master with Slave functions.
• Multiple I2C slave addresses supported in hardware.
• One slave address can be selectively qualified with a bit mask or an address range in
order to respond to multiple I2C-bus addresses.
• 10-bit addressing supported with software assist.
• Supports SMBus.
• Activity on the I2C in slave mode allows wake-up from deep-sleep mode on any
enabled interrupt.
10.17.4.4 USART
Features
• Excluding delays introduced by external device and PCB, the maximum bit rates of
6.25 Mbit/s in asynchronous mode.
• Excluding delays introduced by external device and PCB, the maximum supported bit
rate for USART master synchronous mode is 20 Mbit/s, and the maximum supported
bit rate for USART slave synchronous mode is 20.0 Mbit/s.
• 7, 8, or 9 data bits and 1 or 2 stop bits.
• Synchronous mode with master or slave operation. Includes data phase selection and
continuous clock option.
• Multiprocessor/multidrop (9-bit) mode with software address compare.
• RS-485 transceiver output enable.
• Autobaud mode for automatic baud rate detection
• Parity generation and checking: odd, even, or none.
• Software selectable oversampling from 5 to 16 clocks in asynchronous mode.
• One transmit and one receive data buffer.



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