ADA4622-2ACPZ-R7 datasheet(37/38 Pages) AD

37 / 38 page

Data Sheet

ADA4622-1/ADA4622-2/ADA4622-4

Rev. E | Page 37 of 38

*COMPLIANT TO JEDEC STANDARDS MO-220-WGGC-3

WITH EXCEPTION TO THE EXPOSED PAD.

0.65

BSC

4.10

4.00 SQ

3.90

0.50

0.40

0.30

0.80

0.75

0.70

0.05 MAX

0.02 NOM

0.20 REF

0.20 MIN

COPLANARITY

0.08

PIN 1

INDICATOR

0.35

0.30

0.25

*2.40

2.35 SQ

2.30

BOTTOM VIEW

TOP VIEW

SIDE VIEW

EXPOSED

PAD

SEATING

PLANE

PIN 1

INDIC ATOR AREA OPTIONS

(SEE DETAIL A)

DETAIL A

(JEDEC 95)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

Figure 108. 16-Lead Lead Frame Chip Scale Package [LFCSP]

4 mm × 4 mm Body and 0.75 mm Package Height

(CP-16-20)

Dimensions shown in millimeters

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-012-AB

6.20 (0.2441)

5.80 (0.2283)

4.00 (0.1575)

3.80 (0.1496)

8.75 (0.3445)

8.55 (0.3366)

1.27 (0.0500)

BSC

SEATING

PLANE

0.25 (0.0098)

0.10 (0.0039)

0.51 (0.0201)

0.31 (0.0122)

1.75 (0.0689)

1.35 (0.0531)

0.50 (0.0197)

0.25 (0.0098)

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

COPLANARITY

0.10

8°

0°

45°

Figure 109. 14-Lead Standard Small Outline Package [SOIC_N]

(R-14)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model1

Temperature Range

Package Description

Package Option

Marking Code

ADA4622-1ARJZ-R2

−40°C to +125°C

5-Lead Small Outline Transistor Package [SOT-23]

RJ-5

A3J

ADA4622-1ARJZ-R7

−40°C to +125°C

5-Lead Small Outline Transistor Package [SOT-23]

RJ-5

A3J

ADA4622-1ARJZ-RL

−40°C to +125°C

5-Lead Small Outline Transistor Package [SOT-23]

RJ-5

A3J

ADA4622-1ARZ

−40°C to +125°C