Data Sheet

ADM7151

Rev. B | Page 15 of 24

THEORY OF OPERATION

The ADM7151 is an adjustable, ultralow noise, high power

supply rejection ratio (PSRR) linear regulator targeting radio

frequency (RF) applications. The input voltage range is 4.5 V to

16 V, and it can deliver up to 800 mA of output current. Typical

shutdown current consumption is 0.1 µA at room temperature.

Optimized for use with 10 µF ceramic capacitors, the ADM7151

provides excellent transient performance.

VREG

GND

VOUT

VIN

EN

REF

REF_SENSE

REFERENCE

SHUTDOWN

ACTIVE

RIPPLE

FILTER

SHORT CIRCUIT,

THERMAL

PROTECT

OTA

E/A

BYP

Figure 48. Adjustable Output Voltage Internal Block Diagram

Internally, the ADM7151 consists of a reference, an error amplifier,

a feedback voltage divider, and a P-channel MOSFET pass

transistor. Output current is delivered via the PMOS pass

device, which is controlled by the error amplifier. The error

amplifier compares the reference voltage with the feedback

voltage from the output and amplifies the difference. If the

feedback voltage is lower than the reference voltage, the gate

of the PMOS device is pulled lower, allowing more current to

pass and increasing the output voltage. If the feedback voltage

is higher than the reference voltage, the gate of the PMOS

device is pulled higher, allowing less current to pass and

decreasing the output voltage.

By heavily filtering the reference voltage, the ADM7151 is able

to achieve 1.7 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output

noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7151 architecture uses an internal active ripple filter. This

stage isolates the low output noise LDO from noise on VIN.

The result is that the ADM7151 PSRR is significantly higher

over a wider frequency range than any single stage LDO.

The ADM7151 output voltage can be adjusted between 1.5 V

and 5.1 V and is available in two models that optimize the input

voltage and output voltage ranges to keep power dissipation as

low as possible without compromising PSRR performance. The

output voltage is determined by an external voltage divider

according to the following equation:

VOUT

REF

REF_SENSE

GND

VIN

EN

BYP

VREG

ADM7151-04

10µF

1µF

1µF

1kΩ < R2 < 200kΩ

10µF

10µF

OFF

ON

R1

R2

Figure 49. Typical Adjustable Output Voltage Application Schematic

The R2 value must be greater than 1 kΩ to prevent excessive

loading of the reference voltage appearing on the REF pin. To

minimize errors in the output voltage caused by the REF_SENSE

pin input current, the R2 value must be less than 200 kΩ. For

example, when R1 and R2 each equal 200 kΩ, the output

voltage is 3.0 V. The output voltage error introduced by the

REF_SENSE pin input current is 10 mV or 0.33%, assuming a

maximum REF_SENSE pin input current of 100 nA at 125°C.

The ADM7151 uses the EN pin to enable and disable the VOUT

pin under normal operating conditions. When EN is high, VOUT

turns on, and when EN is low, VOUT turns off. For automatic

startup, EN can be tied to VIN.

VREG

VIN

REF_SENSE

REF

OUT

BYP

GND

EN

18V

6V

6V

6V

6V

6V

6V

6V

6V

18V

18V

Figure 50. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 50).