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ADM7154ACPZ-1.2-R7 数据表(PDF) 6 Page - Analog Devices

部件名 ADM7154ACPZ-1.2-R7
功能描述  600 mA, Ultralow Noise, High PSRR, RF Linear Regulator
PDF  23 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADM7154ACPZ-1.2-R7 数据表(HTML) 6 Page - Analog Devices

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ADM7154
Data Sheet
Rev. B | Page 6 of 23
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
3
BYP
4
GND
1
VREG
2
VOUT
6 REF
5 REF_SENSE
8 VIN
7 EN
ADM7154
TOP VIEW
(Not to Scale)
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
THE EP TO THE GROUND PLANE ON THE BOARD TO
ENSURE PROPER OPERATION.
Figure 3. 8-Lead LFCSP Pin Configuration
ADM7154
TOP VIEW
(Not to Scale)
VREG 1
VOUT 2
BYP 3
GND 4
VIN
8
EN
7
REF
6
REF_SENSE
5
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES
THERMAL PERFORMANCE, AND IT IS ELECTRICALLY
CONNECTED TO GND INSIDE THE PACKAGE. CONNECT
THE EP TO THE GROUND PLANE ON THE BOARD TO
ENSURE PROPER OPERATION.
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
VREG
Regulated Input Supply Voltage to LDO Amplifier. Bypass VREG to GND with a 10 µF or greater
capacitor.
2
VOUT
Regulated Output Voltage. Bypass VOUT to GND with a 10 µF or greater capacitor.
3
BYP
Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to GND to reduce noise. Do not
connect a load to ground.
4
GND
Ground Connection.
5
REF_SENSE
Reference Sense. Connect Pin 5 to the REF pin. Do not connect Pin 5 to VOUT or GND.
6
REF
Low Noise Reference Voltage Output. Bypass REF to GND with a 1 µF capacitor. Short REF_SENSE to REF
for fixed output voltages. Do not connect a load to ground.
7
EN
Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
8
VIN
Regulator Input Supply Voltage. Bypass VIN to GND with a 10 µF or greater capacitor.
EP
Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad enhances
thermal performance, and it is electrically connected to GND inside the package. Connect the EP to the
ground plane on the board to ensure proper operation.



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